Abstract: Techniques are provided for fabricating a three-dimensional, charge-trapping memory device with improved long term data retention. A corresponding three-dimensional, charge-trapping memory device is also provided which includes a stack of alternating word line layers and dielectric layers. A charge-trapping layer is deposited in a memory hole. The refractive index of portions of the charge-trapping layer which are adjacent to the word line layers is increased relative to the refractive index of portions of the charge-trapping layer which are adjacent to the dielectric layers. This can be achieved by doping the portions of the charge-trapping layer which are adjacent to the word line layers. In one approach, the charge-trapping layer is SiON and is doped with Si or N. In another approach, the charge-trapping layer is HfO and is doped with Hf. In another approach, the charge-trapping layer is HfSiON and is doped with Hf, Si or N.

Abstract: A mass storage memory system and method of operation are disclosed. The memory system includes an interface adapted to receive data from a host system, a plurality of memory die and a controller, where the controller is configured to read or write data synchronously across a plurality of die connected to different channels based on a first command, and to read or write data asynchronously and independently in different die in the same channel based on a second command. The controller may program data in a maximum unit of programming for a single memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.

Abstract: Methods and apparatuses for applying different voltages to an I/O interface (such as to the pads of the I/O interface) and determining the data integrity of communicating data (either transmitting to or receiving data from) to another device is disclosed. Data integrity may be measured in one of several ways, such as the window (or timing) at which data can be transmitted correctly using the different voltages. The determined data integrity may be compared with a minimum data integrity, such as a minimum window. In the event that the determined data integrity is greater or better than the minimum data integrity, then the voltage may be reduced and the data integrity determination may be performed again. In this way, the voltage applied to the I/O interface may be reduced while still meeting the minimum data integrity requirements.

Abstract: Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant (low-k) material such as low-k film portions or air. An insulation layer such as SiO2 is etched to form raised structures. The structures are slimmed and a low-k material or sacrificial material is deposited. A further etching removes the material except for portions on sidewalls of the slimmed structures. A metal barrier layer and seed layer are then deposited, followed by a metal filler such as copper. Chemical mechanical polishing (CMP) removes portions of the metal above the raised structures, leaving only portions of the metal between the raised structures as spaced apart conductive lines. The sacrificial material can be removed by a thermal process, leaving air gaps. The raised structures provide strength while the air gap or other low-k material reduces capacitance.

Abstract: A data storage device includes a write cache, a non-volatile memory, and a controller coupled to the write cache and to the non-volatile memory. The controller is configured to, responsive to receiving a command to flush particular data from the write cache, attempt to fill a write block of data using the particular data and pending data obtained after receipt of the command.

Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Abstract: Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache associated with the virtual machine.

Abstract: Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is detected on the bus. A delayed data clock having the selected delay relative to the peripheral clock may be generated. Requested data may be provided on the bus in response to an edge of the delayed data clock.

Abstract: A memory system and method for power-based operation scheduling are provided. In one embodiment, a memory system begins to perform a plurality of operations in an order in which they are stored in a queue. Before performing a next operation in the queue, the memory system determines whether the power consumed by performing the next operation would exceed a maximum power threshold. In response to determining that the power consumed would exceed the maximum power threshold, the memory system selects an operation out of order from the queue to perform instead, so the maximum power threshold would not be exceeded. Other embodiments are provided.

Abstract: A storage module and method are provided for optimized power utilization. In one embodiment, a storage module is provided comprising a storage controller and a plurality of memory dies in communication with the storage controller. The storage controller determines if sufficient power is available to perform an operation on one of the memory dies. In response to determining that sufficient power is not available to perform the operation on one of the memory dies, the storage controller determines if suspending an in-progress operation on another one of the memory dies would provide enough power to perform the operation. In response to determining that suspending the in-progress operation would provide enough power to perform the operation, the storage controller suspends the in-progress operation and performs the operation. Instead of suspending an in-progress operation, the storage controller can instead use a reduced power version of the operation or the in-progress operation.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: A system, method and apparatus for making a semiconductor die includes forming multiple semiconductor devices in a respective portion of a semiconductor wafer. An electrical interconnect structure is formed over the semiconductor devices and provide electrical connections to the semiconductor devices. The electrical interconnect structure including one or more metallization layers. Each of the metallization layers includes conductive lines. At least one portion of at least one of the metallization layers includes a density of the conductive lines that varies as compared to the other portions of the metallization layers. At least one support structure is formed in the electrical interconnect structure. The semiconductor wafer can be a thinned semiconductor wafer.

Abstract: A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell can occur because of coupling based on charge stored by adjacent cells. To account for the shift, compensations can be applied to an adjacent word line when reading based on the different possible conditions of an adjacent cell. The effects of coupling may be more pronounced for memory cells in lower states corresponding to lower threshold voltages. A compensation pass bias can be reduced as the state being sensed at a selected word line increases to account for the different effects. A compensation pass bias for an adjacent word line may be reduced with the application of larger read reference voltages to a selected word line. Other variations to a compensation pass bias are provided.

Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Abstract: A system and method of writing data to a memory block includes receiving user data in a memory controller to be written to the memory block. The user data is first written to a buffer. A screening pattern is written to at least one screening column and a first memory integrity test is performed based on at least one operational aspect of the memory block. The first memory integrity test includes reading screening column data from the at least one screening column and comparing the screening column data read from the at least one screening column to the screening pattern. The user data is written to at least one user data column in the memory block when the screening column data read from the at least one screening column matches the screening pattern in the first memory integrity test.

Abstract: A multiple junction thin film transistor (TFT) is disclosed. The body of the TFT may have an n+ layer residing in a p? region of the body. The TFT may have an n+ source and an n+ drain on either side of the p? region of the body. Thus, the TFT has an n+/p?/n+/p?/n+ structure in this example. The n+ layer in the p? region increases the breakdown voltage. Also, drive current is increased. The impurity concentration in the n+ layer in the p? body and/or thickness of the n+ layer in the p? body may be tuned to increase performance of the TFT. In an alternative, the body of the TFT has a p+ layer residing in an n? region of the body. The TFT may have a p+ source and a p+ drain on either side of the p? region of the body.

Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.