Abstract: A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer.

Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described.

Abstract: A storage module and method for identifying hot and cold data are provided. The storage module can be removable from a host or can be embedded in a host. In one embodiment, a request to store data in a logical block address (LBA) of a memory of the storage module is received. A physical block associated with the LBA is determined, and it is also determined whether the physical block stores hot or cold data. A last-known open block is then selected, wherein the last-known open block is either hot or cold depending on whether the physical block stores hot or cold data. If space is available in the last-known open block, the data is written to the last-known open block.

Abstract: A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of segments. Riser for a pair of segments from each adjacent stacks at different memory layers is provided by a conductive sidewall layer of a stairwell disposed between the adjacent stacks. Multiple insulated conductive sidewall layers provide multiple risers for the adjacent stacks. Layer-by-layer stairwell excavation and sidewall processes between adjacent stacks create risers for different pairs of segments between stacks to form the staircase word lines.

Abstract: An electronic device may receive a supply voltage from another external device, and detect when a level of the supply voltage drops below a threshold. In response, a controller of the electronic device may deactivate an interface configured for communication with the other electronic device. The controller may manage time periods and time period counters to determine when the check whether to reactivate the interface or conclude that the other external device is non-compliant.

Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.

Abstract: A data storage device includes a memory, a controller, and a communication bus coupled to the memory and to the controller. The controller is configured to send a read-write command and write data to the memory via the communication bus. The read-write command indicates an address of requested data to be read from the memory. The controller is further configured to receive the requested data read from the memory. Communicating the requested data over the communication bus overlaps the write data being stored into the memory.

Abstract: A data storage device includes a memory. A method includes de-allocating a first region of a group of regions of the memory during a wear leveling process based on a determination that the first region is associated with a first tag of a set of tags. Each region of the group of regions is assigned to a tag of the set of tags based on a health metric associated with the region. The health metric is based on a bit error rate (BER), a program/erase cycle (PEC) count, a PEC condition metric, or a combination thereof. In response to selecting the first region, information is copied from the first region to a second region of the memory during the wear leveling process.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types. A controller managing the flash memory die is configured to identify an idle die and determine if a layer in the die satisfies a background maintenance criterion. Upon identifying a layer satisfying the background maintenance criterion, the valid data from reclaim blocks in the layer is relocated into a relocation block in the same layer until the relocation block is filled and the background maintenance cycle ends.

Abstract: A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information.

Abstract: Low complexity partial parallel architectures for performing a Fourier transform and an inverse Fourier transform over subfields of a finite field are described. For example, circuits to perform the Fourier transforms and the inverse Fourier transform as described herein may have architectures that have simplified multipliers and/or computational units as compared to traditional Fourier transform circuits and traditional inverse Fourier transform circuits that have partial parallel designs. In a particular embodiment, a method includes, in a data storage device including a controller and a non-volatile memory, the controller includes an inverse Fourier transform circuit having a first number of inputs coupled to multipliers, receiving elements of an input vector and providing the elements to the multipliers. The multipliers are configured to perform calculations associated with an inverse Fourier transform operation.

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Abstract: A mass storage memory system and method of operation are disclosed. The memory system includes an interface adapted to receive data from a host system, a plurality of memory die and a controller, where the controller is configured to read or write data synchronously across a plurality of die connected to different channels based on a first command, and to read or write data asynchronously and independently in different die in the same channel based on a second command. The controller may program data in a maximum unit of programming for a single memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.

Abstract: A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ?MAX.

Abstract: A memory system or flash card may include an algorithm or process for managing the handling of large tables in memory. A delta may be used for each table to accumulate updates. There may be a plurality of deltas for a multi-level delta structure. In one example, the first level delta is stored in random access memory (RAM), while the other level deltas are stored in the flash memory. Multiple-level deltas may improve the number of flash writes and reduce the number and amount of each flush to the actual table in flash. The use of multi-level deltas may improve performance by more efficiently writing to the table in flash.

Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

Abstract: A storage device and method for enabling hidden functionality are provided. In one embodiment, a storage device is provided comprising an interface a memory, and a controller. The controller is configured to receive a series of read and/or write commands to the memory from the host device. If the series of read and/or write commands received from the host device matches an expected pattern of read and/or write commands, irrespective what data is being read or written by those commands, the controller enables a special functionality mode of the storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Non-volatile memory systems with multi-write direction memory units are disclosed. In one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning with an initial word line of the memory block or a last word line of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.

Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.