Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.

Abstract: A non-volatile memory system utilizes multiple programming cycles to write units of data, such as a logical page of data, to a non-volatile memory array. User data is evaluated before writing to determine whether programming can be skipped for bay addresses. The system determines whether programming can be skipped for an initial set of bay groups. If a bay group cannot be skipped, the system determines whether the bay group includes individual bays that may be skipped. Bays are regrouped into new bay groups to reduce the number of BAD cycles during programming. Independent column addressing for multiple bays within a bay group is provided. During a column address cycle, a separate column address is provided to the bays to select different columns for programming within each bay. By simultaneously programming multiple column addresses during a single column address cycle, the system may skip programming for some column address cycles.

Abstract: Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

Abstract: Reduced errors when sensing non-volatile memory are provided by applying a current spike or preconditioning current for a group of memory cells included a selected cell. During a sense operation, a preconditioning current can be passed through a group of non-volatile memory cells. The preconditioning current is provided prior to applying at least one reference voltage to a selected word line. The preconditioning current may simulate a cell current passing through the channel during a verification phase of programming. The preconditioning current can modify a channel resistance to approximate a state during verification to provide a more stable threshold voltage for the memory cells. Preconditioning currents may be applied selectively for select reference levels, select pages, and/or select operations. Selective application of preconditioning currents based on temperature is also provided.

Abstract: Techniques are provided for non-volatile storage self-detecting that a heating event has occurred to the non-volatile storage. One example of the heating event is an Infrared (IR) reflow process. In one aspect, a block of memory cells in a memory device are put through a number of program/erase cycles. A group of the memory cells in the cycled block are programmed to a reference threshold voltage distribution. Some time may pass after programming the cycled block. The memory device self-detects that there has been a heating event in response to a shift in the reference VT distribution being more than an allowed amount. The memory device may switch from a first programming mode to a second programming mode in response to detecting that the heating event has occurred.

Abstract: A sensor that can provide multiple resolutions, based on the output of the same analog-to-digital converter is disclosed. Some applications require a fast measurement of a physical parameter (e.g., temperature, voltage, pressure), but can tolerate a lower resolution measurement. Other applications require a higher resolution measurement, but can tolerate a slower measurement. The sensor may comprise a sigma delta modulator (SDM) ADC that outputs a digital reading. The output may comprise a bus having a width that is equal to the desired highest resolution of the digital code for the physical parameter. The sensor may further comprise a storage unit for each desired level of resolution. The sensor may further comprise logic that causes the storage units to sample the output bus after a certain number of clock cycles in order to store a digital code having a number of bits equal to the resolution.

Abstract: A non-volatile memory is described that includes a sense amplifier that maintains a bit line voltage and output of the sense amplifier at a substantially constant voltage during read operations. During a preset phase, an output of the sense amplifier that is coupled to a selected bit line is grounded. At least one capacitor is precharged during the preset phase. During a sense phase, the sense amplifier output is disconnected from ground while the memory array is biased for reading a selected memory cell. A resulting cell current is integrated by the at least one capacitor. The integrated cell current discharges a sense node from the precharge level to an accurate voltage level based on the resulting cell current.

Abstract: Disclosed herein are techniques for generating a temperature independent reference current, which may be used during calibration. The temperature independent reference current may be generated based on a current through an on-chip calibration resistor. This alleviates the need for an off chip calibration resistor, which can be costly and cause slow calibration. A voltage at one terminal of the on chip calibration resistor may be modulated to substantially cancel a temperature coefficient of the on chip calibration resistor. This may result in the current passing through the on chip calibration resistor being temperature independent. The temperature independent reference current may be based on a reference voltage and a target calibration resistance.

Abstract: Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, the sensing circuitry includes left and right hand portions which have separate cache access lines, but are connected to a common output bus. A full data word can be output at a time by using a half word from the left hand portion and a half word from the right hand portion. Or, the sensing circuitry can be configured so that a full data word is output at a time from the left or right hand portion. One implementation provides an N-bit bus and N input paths for each of the left and right hand portions. Another implementation provides an N-bit bus and N/2 input paths for each of the left and right hand portions.

Abstract: A system and method that allows idle process logic blocks in a memory device to be utilized when the idle process logic blocks would otherwise be remaining idle as the current memory commands are executed. Utilizing the otherwise idle process logic blocks in the memory device allows more optimized use of the process logic blocks while not slowing or otherwise interfering with the execution of the current memory commands. The otherwise idle process logic blocks can perform additional operations for subsequently fetched memory commands that may otherwise cause delays in execution of the subsequently fetched memory commands.

Abstract: Devices and methods implemented therein in are disclosed for correcting errors in data. The method comprises determining that a first copy of data and a second copy of data include errors uncorrectable by an error correction code (ECC) engine. The ECC engine is modified based on determining that the first copy of data and the second copy of data include errors uncorrectable by the ECC engine and using the modified ECC engine, the first copy of data and the second copy of data are processed to correct the errors in the first and second copy of the data.

Abstract: In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in the token bucket by an amount of power consumed over the time period as indicated by the average amount of power sensed by the sensor over the time period.

Abstract: According to one embodiment, a temperature sensor includes: a voltage generating part generating (2N?1)-midpoint voltages (N is a natural number equal to or larger than 2) based on a reference voltage which does not depend on a temperature; a sense part generating a temperature sensing voltage which depends on the temperature; and an arithmetic part is configured to generate N-bit temperature data by executing first to N-th operations each comparing the temperature sensing voltage with one of the (2N?1)-midpoint voltages.

Abstract: High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.

Abstract: A cache automation module detects the deployment of storage resources in a virtual computing environment and, in response, automatically configures cache services for the detected storage resources. The automation module may detect new storage resources by monitoring storage operations and/or requests, by use of an interface provided by virtualization infrastructure, and/or the like. The cache automation module may deterministically identify storage resources that are to be cached and automatically caching services for the identified storage resources.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for key-value stores with partial data access. An interface module is configured to receive a data object for storage in a key-value store. The data object may include a key and a value. A block object module is configured to generate a plurality of block objects smaller than the data object. A block object may include a new key and a new value. The new key may be based on the key for the data object and on metadata for the new value. The new value may be based on at least a portion of the value for the data object. A storage module is configured to store the block objects in the key-value store.

Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

Abstract: An apparatus, system, and method are disclosed for storage address translation. The method includes storing, in volatile memory, a plurality of logical-to-physical mapping entries for a non-volatile recording device. The method includes persisting a logical-to-physical mapping entry from the volatile memory to recording media of the non-volatile recording device. The logical-to-physical mapping entry may be selected for persisting based on a mapping policy indicated by a client. The method includes loading the logical-to-physical mapping entry from the recording media of the non-volatile recording device into the volatile memory in response to a storage request associated with the logical-to-physical mapping entry.

Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.