Abstract: A switching rectifier circuit includes a pulse width modulation controller, a voltage switching circuit, a pulse width modulation comparator, an error amplifier, a voltage reference, a high threshold voltage comparator and a low threshold voltage comparator. A varying output voltage of the voltage regulator is sampled and compared to a high threshold voltage reference and a low threshold voltage reference. When the sampled output voltage is equal to or greater than the high threshold voltage reference the output voltage is decreased. When the sampled output voltage is equal to or less than the low threshold voltage reference the output voltage is increased.

Abstract: A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than then prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type. The method may include the steps of directing host data directly into a particular partition of a particular layer of the multi-layer memory upon receipt depending on a type of the data. The method may also include copying data within the same partition in a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer and in the same partition, as well as transferring data from one layer to the next higher bit per cell layer within a same partition when layer transfer criteria are met.

Abstract: A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.

Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.

Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, each global bit line having a long axis, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width and a thickness. Vertically-oriented bit line select transistors disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. The width of each vertically-oriented bit line select transistor is greater than the thickness of the vertically-oriented bit line select transistors.

Abstract: A non-volatile storage system includes an impedance code calibration circuit. The device has a first variable impedance circuit and a second variable impedance circuit coupled to a calibration node. The device has a control circuit configured to access a previous impedance code for a previous impedance calibration and to divide the previous impedance code into a main impedance code and a remainder impedance code. The control circuit is configured to perform a search for a new impedance code starting with the main impedance code applied to the first variable impedance circuit while maintaining the remainder impedance code to the second variable impedance circuit. The control circuit is configured to add the final impedance code for the first variable impedance circuit with the remainder impedance code to produce a new impedance code for the impedance calibration.

Abstract: Apparatus and method for writing data directly to multi-level cell (MLC) memory without folding or transferring of the data from single-level cell (SLC) memory to MLC memory are disclosed. A memory device, which includes the SLC memory and MLC memory, receives data from a host device. The memory device programs the data (such as the lower/middle/upper pages) from volatile memory into MLC memory, without transferring data from SLC memory. The memory device also stores part of the data (such as the lower/middle pages) in SLC memory as a backup in case of error. In particular, if the data is not properly programmed into the MLC memory, the data in SLC memory is used to program the data a second time into the MLC memory.

Abstract: A method is provided for programming non-volatile memory cells. The non-volatile memory cells are accessible by a plurality of word lines. The method includes using a four-pass programming technique to program a block of the non-volatile memory cells.

Abstract: Detecting defects in select gates of memory cell strings is disclosed. An electrical short between adjacent select gates may be detected. The select gate may comprises a transistor having an adjustable threshold voltage. An operation configured to change a threshold voltage of one select transistor and to maintain a threshold voltage of an adjacent select transistor may be performed. The select transistors may be flagged in response to the threshold voltage of either select transistor failing to meet a target threshold voltage in response to the operation. The operation may be an erase operation or a program operation.

Abstract: A memory system and method for power management are disclosed. In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in the token bucket by an amount of power consumed over the time period as indicated by the average amount of power sensed by the sensor over the time period. Other embodiments are disclosed.

Abstract: A method of forming a NAND flash memory includes etching between word lines to expose isolation material in shallow trench isolation (STI) trenches while active areas between word lines remain covered, then forming protective sleeves at locations over exposed isolation material. Subsequently, with the protective sleeves in place, isotropic etching of isolation material forms an air gap extending continuously between the protective sleeves along an individual STI trench.

Abstract: A nitridation step applied to a tungsten via in a first silicon oxide layer forms a tungsten nitride layer on an exposed top surface of the tungsten via. Subsequently, a second silicon oxide layer is formed over the first silicon oxide layer and the tungsten via. Subsequently, an opening is formed through the second silicon oxide layer to expose at least part of the silicon nitride layer. Subsequently, a wet clean step is performed.

Abstract: Methods and apparatuses for performing receive and transmit path tuning of a toggle mode interface between a primary controller and a secondary controller is disclosed. A first component having a variable setting and connected with a data bus of the interface is iteratively adjusted. For each setting of the first component, test data written to the secondary controller and a delay unit having a variable delay setting and connected with a strobe line of the interface is adjusted. Delay settings are identified where the read data is equal to the written data. Settings for the first component and corresponding delay setting that produce the largest range of delay settings where the read data is equal to the written data is selected. The first component may correspond to a driver unit in the primary controller or an ODT unit in the secondary controller.

Abstract: A dielectric layer extending over a substrate has alternating first and second trenches extending in a first direction. The first trenches have a first shape in cross section along a plane that is perpendicular to the first direction and the second trenches have a second shape in cross section along the plane. Bit lines are located in at least the first trenches.

Abstract: Dummy bit lines of are formed in a sacrificial layer at locations where bit lines are to be formed, with bit lines separated by trenches that extend through the sacrificial layer. Enclosed air gap structures are formed in the trenches between the dummy bit lines. Subsequently, the dummy bit lines are replaced with metal to form bit lines.

Abstract: Techniques are presented for improving the efficiencies of multi-stage charge pumps by reducing the amount of voltage lost across the inter-stage transfer switches of the pump through use a selective body bias. The voltage level from both branches of one stage is each supplied though a corresponding diode to the bulk connection of the transfer switch after the subsequent stage in both branches. This arrangement results in each stage providing a largely uniform amount of gain, without the usual increase of voltage drop with increasing numbers of stages.

Abstract: A mobile device case and method for use therewith are provided. In one embodiment, a mobile device case is provided with a controller configured to detect that the mobile device case was possibly removed from the mobile device and provide an indicator to a mobile device accordingly. In another embodiment, a mobile device is provided comprising a controller configured to send a request to a mobile device case for a listing of the stored in a memory of the mobile device case, receive the listing of data from the mobile device case, and categorize the data into different categories. Other embodiments are provided.

Abstract: An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices.

Abstract: Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, a predefined subset of word lines includes source-side and drain-side word lines. For the predefined subset of word lines, word line voltages are ramped down before the voltages of the select gates are ramped down. Subsequently, for a remaining subset of word lines, word line voltages are ramped down, but no later than the ramping down of the voltages of the select gates. The timing of the ramp down of the selected word line depends on whether it is among the predefined subset or the remaining subset. The predefined subset can include a number of adjacent or non-adjacent word lines.

Abstract: A host power-on reset control circuit includes a comparator connected to receive both a divided version of a supply voltage and a reference voltage. The comparator generates and outputs a high digital state signal when the divided version of the supply voltage is at least as large as the reference voltage. The control circuit includes an output node connected to transmit a power-on reset control signal. The control circuit includes pulldown circuitry connected between the comparator output and the output node. The pulldown circuitry maintains the output node at a reset voltage level as the supply voltage rises to a host operational level, based on a signal present at the comparator output. The control circuit includes pullup circuitry connected between the supply voltage and the output node. The pullup circuitry maintains the output node at a non-reset voltage level after the supply voltage has risen to the host operational level.