Abstract: A data storage device and method for dynamic prediction of random read with low memory consumption are provided. In one embodiment, a data storage device comprises a volatile memory, a non-volatile memory, and a controller. The controller is configured to allocate an amount of space in the volatile memory for a history pattern matcher data structure used to predict next read commands from a host to read data stored in the non-volatile memory; determine an accuracy of the predicted next read commands; and based on the determined accuracy, dynamically allocate a different amount of space in the volatile memory for the history pattern matcher data structure. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device and method are provided for host multi-command queue grouping based on write-size alignment in a multi-queue-depth environment. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to provide a host with an indication of a required amount of data needed to program a set of multi-level cell blocks in the memory; receive an assurance from the host that the host will be providing the data storage device with the required amount of data; and based on the assurance received from the host, program the set of multi-level cell blocks as data is received from the host but before the required amount of data is received from the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device including a biometric reader for biometric authentication to enable access to a storage medium. The data storage device is configured for remote registration of a remote user of the data storage device, wherein registration includes receiving a record of a biometric authentication data set of the remote user from a secure database. Alternatively, a secure authorizing command is received remotely from an authorization server to enable the data storage device to directly read and store biometric data of the remote user. The data storage device can be unlocked by biometric authentication to enable a host device to access user data in the storage medium.

Abstract: A data storage device and method for memory-die-state-aware host command submission are provided. In one embodiment, a data storage device comprises a memory comprising a plurality of memory dies and a controller. The controller is configured to receive a query from a host for a status of a memory die that will be accessed by a command; determine the status of the memory die; and respond to the query by providing the status of the memory die to the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A solder paste stencil includes, in one embodiment, a substrate defining solder apertures, each aperture wall of each of the solder apertures is coated with a coating material that reduces wetting of a solder paste relative to the aperture walls.

Abstract: The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.

Abstract: A data storage device including, in one implementation, a number of memory die packages disposed on a substrate within the data storage device. Each memory die package has a die density that includes one or more memory dies. The die density of each memory die package is configured to provide an even thermal distribution across the number of memory die packages. The respective die densities of two memory of the die packages are different from each other.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the word lines and the strings and is configured to successively apply one of a series of pulses of a program voltage to each selected one of the word lines to program the memory cells connected thereto during a program operation. The control means is also configured to utilize a time of a preliminary period of the program operation based on the one of the series of pulses of the program voltage being applied. The preliminary period of the program operation is before the series of pulses of the program voltage are applied to each selected one of the plurality of word lines.

Abstract: Technology is disclosed herein for memory device with control circuitry having an efficient floorplan. Control circuitry resides in a control semiconductor die that is bonded to a memory die NAND strings extending in a z-direction. The memory die has bit lines extending across the NAND strings in an x-direction. First column control circuitry is connected to and configured to control a first set of bit lines. Second column control circuitry is connected to and configured to control a second set of bit lines. The second column control circuitry is stacked in an x-direction with the first column control circuitry. The control die also has system control circuitry configured to control the first column control circuitry and the second column control circuitry. The system control circuitry resides in the floorplan beside the stacked column control circuitry to allow for additional routing of electrical connections above the system control circuitry.

Abstract: A memory system comprises a monolithic integration of a NAND die, a MRAM die and one or more control dies positioned in a same semiconductor package for high speed and high density non-volatile data storage. The MRAM die can be operated as a cache for the NAND die or to provide long term data storage for data not cached for the NAND die. In one embodiment, the NAND die comprises a plurality of NAND strings. The MRAM die comprises a MRAM structure. The one or more control dies comprise one or more control circuits for operating the NAND die and the MRAM die.

Abstract: A data storage device includes a host interface for coupling the data storage device to a host system. The data storage device also includes a device memory and a controller. The controller is configured to determine if a retrim is needed for the data storage device. In accordance with a determination that the retrim is needed, the controller is configured to identify a time to initiate a new trim on the data storage device, and cause the new trim on the data storage device at the time identified.

Abstract: Latch-based methods and apparatus for performing neural network weight parity detection on the die of a non-volatile memory (NVM) array to detect bit flip errors within neural network weight data are described, particularly for use with floating point number values. Upon detection of a parity error in a neural network weight, the erroneous weight is set to zero to trim the corresponding neuron from the network, thus preventing the erroneous value from significantly affecting the network, particularly in situations where the bit flip would otherwise affect the magnitude of a floating-point weight value. The exemplary latch-based procedures described herein are linear procedures that do not require logic decisions. Procedures are also described that assess an amount of degradation in the NVM array based on parity bit data collected in the latches. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.

Abstract: A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.

Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

Abstract: A data storage device and method to selectively enable access to stored user data files. The method includes receiving authentication credential from a user and, in response, retrieving a unique user identifier associated with the authentication credential. The stored user data files on the data storage device each has respective data file identifier. The method includes, for each user, enumerating a directory of stored data files where the data file identifier matches the unique user identifier of that user. This enables selective access of files corresponding the user. Multiple users can be registered to the same data storage device and selective access prevents one user from accessing another user's data files.

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

Abstract: This disclosure relates to data storage device (DSD) hardware and, more specifically, to systems and methods for encrypting data stored on a DSD. A DSD comprises a non-volatile storage medium to store multiple file system data objects using block addressing. The multiple file system data objects are addressable by respective ranges of blocks. A device controller is integrated with the DSD and comprises hardware circuitry configured to encrypt data to be stored on the storage medium and decrypt data stored on the storage medium based on different cryptographic keys, and to use each of the different cryptographic keys for one of the ranges of blocks addressing a respective file system data object. The decryption part of the hardware circuitry can be deactivated so that the data can be read in encrypted form.

Abstract: The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. The memory cells are configured to retain a threshold voltage corresponding to memory states. Each one of the strings has drain-side select gate transistors on a drain-side of the one of the strings including top drain-side select gate transistors connected to bit lines and coupled to the memory cells of the-one of the strings. A control means is coupled to the word lines and bit lines and is configured to apply an unselected top voltage to unselected ones of the top drain-side select gate transistors during a memory operation. The control means is also configured to simultaneously apply a selected top voltage to selected ones top drain-side select gate transistors during the memory operation. The unselected top voltage is intentionally different electrically than the selected top voltage.

Abstract: An apparatus is provided that includes a plurality of non-volatile memory cells, a charge pump circuit configured to receive a clock signal and provide a plurality of voltages to the non-volatile memory cells, and a control circuit coupled to the non-volatile memory cells and the charge pump circuit. The control circuit is configured to reduce a current consumed by the apparatus by selectively reducing a clock rate of the clock signal depending on a memory operation being performed on the non-volatile memory cells.