Abstract: Systems, methods, and data storage devices for image grouping in an end user device using trained machine learning group classifiers are described. The end user device may include an image group classifier configured to classify new image data objects using an image classification algorithm and set of machine learning parameters previously trained for a specific image group. The end user device may determine embeddings that quantify features of the target image object and use those embeddings and the image group classifier to selectively associate group identifiers with each new image data object received or generated by the end user device. Calibration, including selection and training, of the image group classifiers and ranking of classified images are also described.

Abstract: A storage system receives a request to read data that is located in a wordline undergoing a program operation. Instead of waiting for the program operation to complete, which would increase read latency, the storage system aborts the program operation and reconstructs the data from successfully-programmed memory cells in the wordline and from data latches associated with unsuccessfully-programmed memory cells in the wordline. The reconstructed data is then sent to the host. The program abort command can be similar to one used to provide a graceful shutdown in a power-loss situation.

Abstract: A data storage device for providing zone management optimization may include memories including staging memory areas (e.g., single level cells) and destination memory areas (e.g., quad-level cells). The destination memory areas may include memory regions (e.g., zones). A controller may be configured to receive data from a host system, write the data initially to the staging memory areas, receive a region full indication for a first memory region. In response to receiving the region full indication, the controller may add a first entry corresponding to the first memory region to a double linked list. The controller may select, using a region selection randomization method, a second entry corresponding to a second memory region, and folds a second data to the second memory region. The first data may be associated with the first memory region and the second data may be associated with the second memory region.

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

Abstract: On memory die and other circuits, some parts may operate at a VDD logic level while other elements operate at a higher logic level, such as at or near the die's supply level VSUP. To reduce power consumption and increase operating speeds, VDD levels are moving to increasingly lower voltages. To raise the logic signal from the lower level to the higher, level shifters can be used. However, as the gap between the supply level VSUP and VDD widens, it can become difficult for a level shifter to reliably raise a logic signal operating at the VDD level to the VSUP level. The address this problem, the following introduces a small charge pump to boost the input logic signals for level shifter circuits to allow them to reliably generate an output logic signal at the VSUP level from an input logic signal at low VDD levels.

Abstract: Systems and methods are disclosed for providing an indication of the data transfer protocol that is operative during a data transfer operation between a data storage device capable of supporting a plurality of data transfer protocols and a host computer. A protocol controller of the data storage device is configured to determine a data transfer protocol based on a data cable used and to generate a selector signal used to provide the indication.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller includes a decoder multiplexer (mux) module, a plurality of request/response channels coupled to the decoder mux module, an arithmetic pipeline module coupled to the plurality of request/response channels, an arbiter module coupled to the plurality of request/response channels and the arithmetic pipeline module, a mux/arbiter module coupled to the arithmetic pipeline module, a random access memory (RAM) access module coupled to the decoder mux module and the mux/arbiter module, and a RAM coupled to the mux/arbiter module. The controller is configured to determine a pipeline depth value and a calculation parallelism value of the arithmetic pipeline module and configure the arithmetic pipeline module based on the determining.

Abstract: To reduce spikes in the current used during read operations by a system of multiple NAND memory dies operated in parallel, relative delays between the memory dies are introduced before high current sub-operations of the read. The occurrence of the primary current peak in the read operation can depend upon the extent to which a selected memory block is programmed. For example, in a closed block the primary peak occurs when ramping up unselected word lines, while for an open block the primary read peak occurs when the bit lines are charged up. To account for these differences, determining where to introduce relative delays is based on the extent to which a block is programmed. For example, if a block fully or largely closed, delays are introduced before ramping up the unselected word lines, but otherwise adding the delays before charging up bit lines.

Abstract: A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: To improve programming performance in NAND memory, while maintaining programming accuracy and reducing program disturb, the channel pre-charge phase before a programming pulse can be eliminated. Instead, a read recovery phase after the program verify directly discharges a selected word line from the verify voltage to a negative word line voltage, with non-selected word lines being directly discharged from the read bypass voltage to the negative word line voltage. From the negative word line voltage, the word lines are then ramped up to ground and then on the bias levels of the following programming pulse. These conditions can drive electrons from the charge storage region of the selected memory cell, resulting in a high degree of channel boosting and much less program disturb. Variations of the technique can be applied to NAND memory operable in a sub-block mode where it can be difficult to use the typical channel pre-charge.

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

Abstract: A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also determines an initial last good page based on the coarse inspection and performs a fine inspection of at least one page based on a second number of bytes greater than the first number of bytes. The fine inspection validates the initial last good page and identifies the initial last good page as an actual last good page of the dirty block.

Abstract: Zoned memory typically requires write commands to be sent from a host to a data storage device in logical block address (LBA) sequential order. Instead of rejecting out-of-order write commands, the data storage device can execute those commands and internally deal with the out-of-order problem. For example, the data storage device can use a special zone logical-to-physical address table, use a temporary zone data buffer, and/or store a data's LBA in a header for later matching.

Abstract: Disclosed herein are apparatuses for nucleic acid sequencing, and methods of making and using such apparatuses. In some embodiments, the apparatus comprises a magnetic sensor array comprising a plurality of magnetic sensors, each of the plurality of magnetic sensors coupled to at least one address line, at least one selector element, and a fluid chamber adjacent to the magnetic sensor array, the fluid chamber having a proximal wall adjacent to the magnetic sensor array. A method of manufacturing sequencing device comprises fabricating a first addressing line on a substrate, fabricating a plurality of magnetic sensors such that the bottom portion of each sensor is coupled to the first addressing line, depositing a dielectric material between the sensors, fabricating additional addressing lines coupled to the top portions of the sensors, and removing a portion of the dielectric material adjacent to the sensors to create a fluid chamber.

Abstract: Disclosed herein is a data storage device. A data port transmits data between a host computer system and the data storage device. A non-volatile storage medium stores encrypted user content data and a cryptography engine connected between the data port and the storage medium uses a cryptographic key to decrypt the encrypted user content data. The access controller generates an authorization request for a manager device. The authorization request comprises a certificate. The certificate comprising key data. In response to receiving the key data in a response to the authorization request generated by the manager device, the access controller generates configuration data based on the key data to register the device to be authorized as an authorized device.

Abstract: The present disclosure generally relates to host memory buffer (HMB) cache management in DRAM-less SSDs. HMB is transient memory and may not always be available. For example, when the link between the data storage device and the host device is not active, the data storage device can't access the HMB. Placing an HMB log in the HMB controller that is disposed in the data storage device provides access to data that would otherwise be inaccessible in the HMB. The HMB log contains any deltas that have occurred since either the last copying to an HMB cache in the memory device or any delta that have occurred since the link became inactive. The HMB cache mirrors the HMB. In so doing, the data of the HMB is available to the data storage device not only when the link is active, but also when the link is not active.

Abstract: A data storage device includes a memory device and a controller. The controller is configured to assert a strobe cycle having a plurality of strobes to the memory device, where a die of the memory device may be associated with one or more strobes of the plurality of strobes. The controller is further configured to determine whether the die of the memory device requires additional power and adjust a strobe length of time of the corresponding strobe when the die of the memory device requires additional power. The controller is further configured to decrease a strobe length of time of one or more strobes that do not require additional power. By utilizing a time division peak power management (TD-PPM) feature by dynamically changing a strobe length of time of each strobe of the plurality of strobes, performance and latency of the data storage device may be improved.

Abstract: Non-volatile memory cells are programmed by pre-charging channels of unselected non-volatile memory cells connected to a selected data word line, boosting the channels of unselected non-volatile memory cells connected to the selected data word line after the pre-charging and applying a program voltage pulse to selected non-volatile memory cells connected to the selected data word line while boosting. The pre-charging includes applying pre-charge voltages to one set of data word lines and dummy word line(s) as well as applying overdrive voltages to another set of data word lines connected to already programmed memory cells. At the end of the pre-charging, the dummy word lines are ramped down to a resting voltage prior to lowering the data word lines to one or more resting voltages.

Abstract: The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of each component. The disclosure proposes modifying the table according to different system environment parameters to maintain performance or reduce power consumption. Adaptive tuning allows a more flexible system design that can adapt according to the current system status. Adaptive tuning also reduces peak power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.

Abstract: A data storage device includes a non-volatile memory device including a memory block including a number of memory dies, and a controller coupled to the non-volatile memory device. A read command is received from an external device and the controller determines whether a read operation associated with the read command is a sequential read operation. One or more relocation operations are performed in response to determining that the read operation is a sequential read operation. The one or more relocation operations are executed in an order based on a priority associated with each of the one or more relocation operations.