Patents Assigned to SanDisk Technologies LLC
  • Publication number: 20250245093
    Abstract: A storage device may recover from an uncorrectable read failure in a control block. The storage device includes a memory device divided into blocks. The blocks on the memory device may include control blocks for storing control information for accessing host data. A controller on the storage device may identify when an uncorrectable read failure occurs in a first control block. The controller may quarantine the first control block and notify a host device of the uncorrectable read failure. Based on a response from the host device, the controller may recover the storage device to operate in a normal mode such that a recovered storage device excludes the first control block from use.
    Type: Application
    Filed: January 25, 2024
    Publication date: July 31, 2025
    Applicant: SanDisk Technologies LLC
    Inventors: KARAN PATEL, AMIT CHOPRA, NITIN JAIN
  • Publication number: 20250239317
    Abstract: A storage device may speed up error correction by pre-characterizing weak cell information in a memory device. The storage device includes a memory device with cells that may store multiple bits. A controller executes a pre-characterization operation on the memory device to identify a slow cell and/or a fast cell on the memory device. The controller retrieves weak cell information for the slow cell and/or the fast cell. The controller converts the weak cell information into values used by an error correction engine and provides the values to the error correction engine to be used in decoding information retrieved from the memory device.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 24, 2025
    Applicant: SanDisk Technologies LLC
    Inventors: ADAM JACOBVITZ, PIYUSH DHOTRE, NILES YANG, JUAN CARLOS LEE, ERAN SHARON, IDAN GOLDENBERG, ZHENNI WAN
  • Publication number: 20250224892
    Abstract: A storage device optimizes die utilization in multi-meta die-based environments. The storage device includes a memory device including multiple meta dies. When a controller on the storage device receives host instructions, the controller selects a first meta die on which to execute the host instruction. If the controller identifies that at least one inactive die is present on the first meta die and that the first meta die has unused bandwidth, the controller selects a second meta die having a pending background operation. The controller transfers the unused bandwidth from the first meta die to the second meta die. The controller executes the background operation on the second meta die, using the unused bandwidth from the first meta die, in parallel with foreground operation on the first meta die.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 10, 2025
    Applicant: SanDisk Technologies LLC
    Inventors: Amit Sharma, Dinesh Kumar Agarwal
  • Publication number: 20250225071
    Abstract: A storage device postpones entry into a read-only mode due to faulty blocks that cannot be written to on a memory device. The memory device is divided into blocks. Blocks used for storing host data are placed in a main area pool, blocks used for storing host data and for peak write operations are placed in a burst pool, and blocks used for storing control information are placed in the control pool. A controller executes a read-only mode extension protocol to determine when a number of faulty blocks in the main area pool, control pool, or burst pool is approaching a threshold for placing the storage device in a read-only mode. If the storage device is approaching the read-only mode, the controller reduces and/or repurposes a number of the blocks used for storing host data in the burst pool to prevent the storage device from entering the read-only mode phase.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 10, 2025
    Applicant: SanDisk Technologies LLC
    Inventors: KARAN PATEL, AMIT CHOPRA, NITIN JAIN
  • Patent number: 12254209
    Abstract: A storage device performs a format operation for host devices using different format times and commands configurations. When a controller on the storage device receives an erase command from a host device, the controller determines the format time and a chunk size associated with data in the erase command. The controller executes a first format operation scheme, a second format operation scheme, or a third format operation scheme to perform an erase operation on the data in the erase command within the format time. The controller halts execution of the erase operation and returns operation to the host device when the format time expires.
    Type: Grant
    Filed: October 25, 2023
    Date of Patent: March 18, 2025
    Assignee: Sandisk Technologies, LLC
    Inventors: Lovish Singla, Ramkumar Ramamurthy, Shaheed Nehal A
  • Patent number: 12229415
    Abstract: In NAND memory, data sanitization allows a relatively small unit of data (e.g., less than a block) to be effectively destroyed by increasing threshold voltages of memory cells from their programmed threshold voltage to the highest threshold state. To reduce the amount of disturb on memory cells not selected for data sanitization, prior to applying a program voltage to a target word line, a hole based pre-charge operation is performed. More specifically, for NAND strings having a memory cell selected for data sanitation, prior to applying a programming pulse to the corresponding word line, a soft erase operation is performed. After biasing the memory cells and select gates of the NAND strings to a low voltage, a soft erase voltage pulse is applied to the source lines and bit line to pre-charge the NAND string channels with holes.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: February 18, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Wei Cao, Jiacen Guo, Xiang Yang
  • Patent number: 12230333
    Abstract: Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: February 18, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Anirudh Amarnath, Aravind Suresh, Abhijith Prakash
  • Patent number: 12205008
    Abstract: A non-volatile memory device is configured for in-memory computation of layers of a neural network by storing weight values as conductance values in memory cells formed of a series combination of a threshold switching selector, such as an ovonic threshold switch, and a programmable resistive element, such as a ReRAM element. By scaling the input voltages (representing inputs for the layer of the neural network) relative to the threshold values of the threshold switching selectors, dropout for inputs can be implemented to reduce overfitting by the neural network.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 21, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Wen Ma, Tung Thanh Hoang, Martin Lueker-Boden
  • Patent number: 12205654
    Abstract: The memory device includes a plurality of memory cells which are arranged in an array. The memory device further includes a plurality of bit lines that are coupled with the memory cells and a controller. The controller is configured to program the memory cells from an erased data state to three programmed data states in a programming operation that includes three programming pulses and zero verify operations using different patterns to dictate the application of inhibit voltages to the bit lines during each of the three programming pulses. The patterns include two pre-established patterns and additional patterns that are derived from the pre-established patterns using logic operations.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: January 21, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Takayuki Inoue, Jiacen Guo
  • Patent number: 12205657
    Abstract: Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: January 21, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Henry Chin, Erika Penzo, Muhammad Masuduzzaman
  • Patent number: 12205658
    Abstract: Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was detected. The memory system can select a next, immediate available erased page and begin one-pulse programming to store the inflight data, without ramping down the program pump and program pulse, which was in use before the power loss event. The existing programming voltage is used to store/program the inflight data via single pulse programming. When power is restored, the inflight data is moved/programmed to another block for good data reliability.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: January 21, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Shantanu Gupta, Amiya Banerjee, Harish Singidi
  • Patent number: 12205638
    Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: January 21, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Nathan Franklin, Ward Parkinson, Michael Grobis, James O'Toole
  • Patent number: 12205640
    Abstract: A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: January 21, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Michael K. Grobis, Daniel Bedau, Christopher J. Petti
  • Patent number: 12190969
    Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings and the strings comprise a plurality of blocks which comprise planes. A control means is configured to program the memory cells connected to one of the word lines and associated with one of the strings in each of the plurality of planes and acquire a smart verify programming voltage individually for each of the planes in a smart verify operation. The control means concurrently programs at least some of the memory cells connected to each of the word lines in each of the planes in a program operation using the smart verify programming voltage individually acquired for each of the planes in the smart verify operation.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: January 7, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Ke Zhang, Liang Li
  • Patent number: 12176037
    Abstract: In a multi-tiered non-volatile memory structure that can perform operations on sub-blocks, performance of the different tiers/sub-blocks is made consistent by using different word line to word line pitches in the different tiers/sub-blocks.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: December 24, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Wei Cao, Jiacen Guo
  • Patent number: 12176032
    Abstract: Different ramp rates for different regions, or zones, of word lines are used for the pass voltage applied to unselected word lines during a program operation. The properties of the word lines, such as their resistance and capacitance (RC) values, vary across the NAND memory array. By determining the RC values of the word lines across the array, the word lines can be broken into multiple zones based on these properties. The zones can then be individually assigned different ramp rates for applying a pass voltage to the unselected word lines, where a parameter for the ramp rates can be stored as a register value on the memory die.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: December 24, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Abu Naser Zainuddin, Jiahui Yuan, Towhidur Razzak
  • Publication number: 20240395328
    Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: SanDisk Technologies LLC
    Inventors: Abhijith Prakash, Anubhav Khandelwal
  • Patent number: 12154630
    Abstract: In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: November 26, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Yi Song, Jiahui Yuan, Yanjie Wang
  • Patent number: 12153801
    Abstract: A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: November 26, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Yihang Liu, Xiaochen Zhu, Jie Liu, Sarath Puthenthermadam, Jiahui Yuan, Feng Gao
  • Patent number: 12148459
    Abstract: Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: November 19, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Ward Parkinson, James O'Toole, Thomas Trent, Nathan Franklin, Michael Grobis, James W. Reiner, Hans Jurgen Richter, Michael Nicolas Albert Tran