Abstract: A storage device may communicate with a host in multiple modes and physically erase data stored on a memory device in each mode. The storage device includes a memory device to store data. A controller on the storage device may receive a first command from the host to erase the data when the storage device communicates with the host in a first mode. The controller may execute the first command in the first mode and set an in-progress bit. The controller may determine when the storage device has switched to communicate with the host in a second mode and may determine that the in-progress bit is set. The controller may provide a first indication to the host, and in response to the first indication, receive a second command from the host. The controller may execute the second command in the second mode to erase the data in the second mode.

Abstract: A method for authenticating a host computer system to access a data storage device (DSD) comprising a non-volatile storage medium including a plurality of blocks, the method comprising: receiving, from a computer program on the host computer system, an initial read request to read a block of the plurality of blocks and in response sending information from the block to the host computer system; iteratively receiving, from the computer program on the host computer system, a subsequent read request to read a subsequent block of the plurality of blocks based on the information sent from the block of a previous response; and in each iteration sending information from the subsequent block to the host computer system or terminating the iterative process in response to determining that each block of the plurality of blocks has been read; and determining the host computer system is authenticated in response to determining one or more conditions are met, wherein the one or more conditions include determining that each

Abstract: A storage device may recover from an uncorrectable read failure in a control block. The storage device includes a memory device divided into blocks. The blocks on the memory device may include control blocks for storing control information for accessing host data. A controller on the storage device may identify when an uncorrectable read failure occurs in a first control block. The controller may quarantine the first control block and notify a host device of the uncorrectable read failure. Based on a response from the host device, the controller may recover the storage device to operate in a normal mode such that a recovered storage device excludes the first control block from use.

Abstract: A non-volatile memory stores data in non-volatile memory cells by programming the non-volatile memory cells to a set of data states. Data stored in the non-volatile memory cells is read by sensing for a set of read reference levels for the data states. The read reference levels are adjusted based on performing sense operations at incrementally higher threshold voltages and counting a number of memory cells newly turning on at each sense operation performed until the sooner of a maximum number of sense operations or the count of number of memory cells newly turning on during a current sense operation is greater than the count of number of memory cells newly turning on during a previous sense operation. The system then identifies a valley in the number of memory cells newly turning on and adjusts one or more read reference levels based on the identified valley.

Abstract: A method and hardware wallet to securely signing a transaction. This includes the hardware wallet receiving, from a host application of a host device, an unsigned transaction and a coin seed associated with a cryptocurrency coin of the unsigned transaction. The hardware wallet generates a private key based on: a root seed stored in the storage medium of the hardware wallet; and the received coin seed. The hardware wallet cryptographically signs the unsigned transaction with the generated private key to generate a signed transaction and sends the signed transaction to the host device.

Abstract: A method for assessing a data access request to a data storage device (DSD) by a computer program, the method comprising: assigning a plurality of queues to a plurality of computer programs, wherein each computer program is configured to authentically access one partition of a plurality of partitions of a non-volatile storage medium of the DSD using one queue of the plurality of queues assigned to that computer program and corresponding to that one partition; receiving, from the computer program, a data access request to access a first partition of the plurality of partitions using a first queue of the plurality of queues; and assessing the data access request by: determining whether the one queue of the plurality of queues corresponding to the first partition is the first queue; and in response to determining the one queue of the plurality of queues corresponding to the first partition is the first queue, determining the first queue is authentic to assess the first partition.

Abstract: A data storage device comprises a data port configured to transceive data between a data source and the data storage device, a non-volatile storage medium, configured to store encrypted user data, and a wireless communication port, configured to wirelessly transceive data between a server application and the data storage device. In response to the operational status of the data storage device being locked, transmit, via the wireless communication port, a security status enquiry message to a server application. Receive, via the wireless communication port, from the server application, a security status of the data storage device, the security status indicating whether the data storage device is registered as being secured or unsecured. Receive, via the data port, an unlock request and, in response to the security status indicating that the data storage device is secured, transition the operational status of the data storage device from a locked state to an unlocked state.

Abstract: A storage device may dynamically adjust a delay time associated with status polling of a memory device. The storage device includes a memory device to store data and to operate on the data based on commands received from the storage device. A controller on the storage device sends a command to the memory device for the memory device to operate on the data based on the command and sends a poll to the memory device to determine when the memory device has completed processing the command. The controller may record a status poll count for the command in a buffer and compute a running average value for status poll counts in the buffer. The controller compares the running average value with a target window and adjusts a delay time between sending another command and another poll based on based on the comparison.

Abstract: A data storage device comprising: a storage medium; a communication interface to enable communication with a host device; and a flash translation layer (FTL) module. The FTL module is configured to: receive a fingerprint key of an enrolled user from a fingerprint sensor; determine selective access restrictions of the enrolled user based on the fingerprint key; and in response, enable the host device selective access to user data in the storage medium in accordance with the selective access restrictions. Selective access is enabled by receiving a corresponding portion of a logical to physical (L2P) table associated with the selective access restrictions of the enrolled user.

Abstract: A data storage device and method are disclosed for defining caching layers based on cache attributes. In one embodiment, a data storage device is provided comprising a non-volatile memory, a plurality of caches, and one or more processors. The one or more processors, individually or in combination, are configured to: receive a command from a host to read data from the non-volatile memory; select a cache from the plurality of caches based on at least one cache attribute other than speed; read the data from the non-volatile memory; and store the data in the selected cache. Other embodiments are provided.

Abstract: In a non-volatile memory system of a memory controller connected to a number of memory dies in which the memory dies use an unmatched architecture for the data input path of the memory dies, the data signals and clock signals from the controller may not align properly when they reach the data latches of the memory die's receiver circuit. To account for possible mis-match, the controller can compensate by individually determining and introducing a corresponding one of multiple relative delay values to the clock signal path. Which delay parameter value is used for each die can be determined based on the power consumed by the memory die when data is transmitted using the different delay values.

Abstract: A storage device may trigger a non-target on-die termination (ntODT) on non-target dies in a memory device. A controller on the storage device may send a command to a target die. When a memory device including the target die and the non-target dies, receives a chip enable (CE) signal, the target die and non-target dies listen to the command. If the communication channel includes one CE bucket, the non-target dies in the CE bucket use the address of the target die to determine that they are non-target dies. If the communication channel includes more than one CE buckets, the non-target dies in a CE bucket that does not include the target die, use a command trigger to determine that they are non-target dies. The non-target dies turn on the ntODT during data transmission and turn off the ntODT when the data transmission is complete.

Abstract: A storage device may detect when data transferred from a memory device is read from a correct physical address on the memory device. The storage device includes a memory device to store data wherein data stored on the memory is accessed by referencing physical addresses on the memory device. A controller on the storage device may send a read instruction to the memory device to read data at a first physical address. When the controller receives the data from the memory device, the controller may descramble the data with a seed based on the first physical address. The seed is supplied by the controller. The controller may also perform a check and determine when an expected value is absent from the data. The controller may detect that the data is read from a second physical address when the controller is unable to retrieve the expected value from descrambled data.

Abstract: A non-volatile storage apparatus includes memory cells that are configured to be programmed into a set of data states defined by current distributions. The same information is stored redundantly in non-volatile memory cells connected to different bit lines of predetermined groups of bit lines. During sensing, output is sensed from the multiple bit lines of a group and averaged to determine a result. For example, to perform vector-matrix multiplication, the system senses current from multiple bit lines of a group of bit lines and determines an average of current flowing on the multiple bit lines within the group while the multiple bit lines are simultaneously receiving current from multiple memory cells storing weight information in response to an input vector.

Abstract: A storage device may communicate with a host in multiple modes and physically erase data stored on a memory device in each mode. The storage device includes a memory device to store data. A controller on the storage device may receive a first command from the host to erase the data when the storage device communicates with the host in a first mode. The controller may execute the first command in the first mode and set an in-progress bit. The controller may determine when the storage device has switched to communicate with the host in a second mode and may determine that the in-progress bit is set. The controller may provide a first indication to the host, and in response to the first indication, receive a second command from the host. The controller may execute the second command in the second mode to erase the data in the second mode.

Abstract: Technology for NAND in-memory computing. Currents from multiple NAND strings may be accumulated in order to improve the signal-to-noise ratio to thereby improve accuracy for in-memory compute using NAND. The memory system may program threshold voltages of memory cells of a number of NAND strings to represent a corresponding number of copies of a first set of values such as a first vector. Voltages may be applied to gates of the memory cells in order to represent a second set of values (e.g., a second vector). The current from each NAND string is accumulated at a sense node resulting in an “accumulated signal.” The foregoing may be applied for another set of NAND strings and another sense node to provide a second accumulated signal. The accumulated signals may be compared to determine a result for an in-memory compute (e.g., vector/vector multiply).

Abstract: Technology for in-memory computing. NAND memory cells are organized into calculation cell units based on one or more physical and/or operational characteristics of the NAND memory cells. Variances in physical and/or operational characteristics of the NAND memory cells in a calculation cell unit can negatively impact accuracy of the in-memory compute. NAND memory cell transistors that are similar to each other in the one or more physical and/or operational characteristics are placed into a calculation cell unit even if those memory cells are not adjacent to each other. Two memory cell transistors of one calculation cell unit may be separated by at least one memory cell transistor of a different calculation cell unit. Organizing NAND memory cell transistors into calculation cell units based on one or more physical and/or operational characteristics improves accuracy of NAND in-memory compute.

Abstract: Technology for NAND in-memory compute. A NAND memory system uses a VGS ladder in which the expected (or estimated) voltage at the source terminal of a particular NAND memory cell transistor is factored into the determination of the voltage to apply to the gate. An estimate may be made of what voltage will be at the source terminal of each NAND memory cell transistor during in-memory computation. The voltage to apply to the gate of the NAND memory cell transistor may then be determined by adding the estimated source terminal voltage to the target VGS. Therefore, the actual VGS is much closer to the target VGS thereby improving accuracy of NAND in-memory compute.

Abstract: An apparatus includes control circuits configured to connect to a plurality of nonvolatile memory cells in NAND strings. The one or more control circuits are configured to apply read voltages on selected word lines to read selected memory cells while read-pass voltages are applied to unselected word lines. The read-pass voltages including a first Near Word Line (NWL) read-pass voltage applied to a first unselected word line adjacent to a selected word line, a second NWL read-pass voltage applied to a second unselected word line adjacent to the selected word line and a common read-pass voltage applied to additional unselected word lines.

Abstract: Technology for in-memory computing. Signal lines used for in-memory computation are organized into signal line pairs based on resistance of the signal lines. Each signal line pair may be used in a multiply and accumulate (MAC) operation. Bit lines in a 3D NAND memory system may be organized into bit line pairs based on resistances of the bit lines. Bit lines having resistances within a tolerance of each other may be placed into a bit line pair. The memory system may determine a result for the MAC based on a difference between two bit line current of bit line pair.