Patents Assigned to Sanmina-SCI
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Patent number: 7631423Abstract: A method is provided for fabricating a multilayer printed circuit board, including embedded electrically conductive elements formed as part of the fabrication of the layers of the printed circuit board. An insulating layer and a conductive layer are then pressed over the electrically conductive elements such that the electrically conductive elements protrude from the surface of the conductive layer. A mechanical process is the applied to remove these protrusions to expose the embedded electrically conductive elements. An electrically conductive undercoat may be applied over the surface of the conductive layer and a second circuit pattern is formed over the electrically conductive undercoat.Type: GrantFiled: February 13, 2006Date of Patent: December 15, 2009Assignee: Sanmina-Sci CorporationInventors: Lim Siong San, Neo Mok Choon, Kevin Lim, Kelvin Yeow, Tan Kwang Chiah
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Publication number: 20090288874Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.Type: ApplicationFiled: June 11, 2009Publication date: November 26, 2009Applicant: SANMINA SCI CORPORATIONInventors: George Dudnikov, JR., Franz Gisin
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Patent number: 7593203Abstract: Protection for sensitive components on a printed circuit board by selectively depositing transient protection material on one or more layers of the printed circuit board is disclosed.Type: GrantFiled: February 16, 2006Date of Patent: September 22, 2009Assignee: Sanmina-SCI CorporationInventors: George Dudnikov, Jr., Franz Gisin, Gregory J. Schroeder
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Patent number: 7542945Abstract: System terminal integrated with biometric sensor, such as a fingerprint sensor. Transaction terminal such as a point of sale system, automated teller machine (ATM) or other system. The system may include a touch screen display. Also, logic to process sales transactions may be included. The transaction terminal may include a cash drawer. The system authenticates users based on data from the sensor, and can regulate access, for example to a cash drawer, based on the authentication. Also described is a sensor module, security system, and method of operating a transaction terminal.Type: GrantFiled: January 15, 2003Date of Patent: June 2, 2009Assignee: Sanmina-SCI CorporationInventors: Gregory K. Thompson, Terry W. Gardner, Jimmy Smith, Ron Mills
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Patent number: 7529287Abstract: An optical system comprises optical pump lasers, depolarizing filters and a multiplexer. A plurality of optical pump lasers generates a plurality of initial optical signals at different wavelengths. A plurality of depolarizing filters depolarize the plurality of initial optical signals. A multiplexer multiplexes the plurality of initial optical signals to form at least one optical pump signal. These systems and methods advantageously provide at least one optical pump signal with the required energy spread across multiple polarizations with fewer optical pump lasers. The reduction of optical pump lasers may eliminate the need to balance or adjust the power and polarization of each optical pump laser. Further, by reducing the number of optical pump lasers, the rate of component failure also reduces. As a result, these systems and methods are more reliable, may reduce maintenance costs, and may reduce the size as well as weight of the optical pumping system.Type: GrantFiled: January 18, 2005Date of Patent: May 5, 2009Assignee: Sanmina-SCI CorporationInventor: Brian Chaput
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Patent number: 7492716Abstract: Network topology codes are computed and used as keys to retrieve topology-specific information for isomorphic networks.Type: GrantFiled: October 26, 2005Date of Patent: February 17, 2009Assignee: Sanmina-SCIInventor: James Wesley Bemont
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Publication number: 20090036167Abstract: A base station system and method for base station heat dissipation using chimneys where the base station system comprises a first structure, an enclosure, and a chimney. The first structure supports base station circuitry that generates heat. The enclosure encloses the first structure and the base station circuitry and forms an internal space. The chimney comprises a second structure forming dedicated space for heat dissipation. The chimney transfers the heat generated by the base station circuitry from the internal space to an external space outside the enclosure.Type: ApplicationFiled: November 29, 2005Publication date: February 5, 2009Applicant: Sanmina-SCI CorporationInventor: Anders Sterner
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Publication number: 20090025213Abstract: The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.Type: ApplicationFiled: October 4, 2008Publication date: January 29, 2009Applicant: SANMINA SCI CORPORATIONInventors: George Dudnikov, JR., Franz Gisin, Gregory J. Schroeder
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Patent number: 7478890Abstract: A rack system for electronic and/or electrical equipment including a frame, a front door mounted to the front of the frame, a back door or panel, two side panels mounted to the back and two sides of the frame, and a top panel mounted to the top of the frame. The doors can be single doors or dual doors. The frame includes a rectangular base frame constructed by four horizontal edge members, and a top frame having the same structure as the base frame, and four vertical members each extending between two associate corners of the base frame and the top frame, and joining the base frame and top frame together. The horizontal members and vertical members are contoured with step-like structures, so that the rack has a high stiffness and strength. The door includes a hinge and a latch attached to two vertical members. The panels are provided with tabs and latches for securing the panels to the frame.Type: GrantFiled: November 30, 2005Date of Patent: January 20, 2009Assignee: Sanmina-Sci CorporationInventors: Andrew Hudz, Peter Jeffery, Zia Shariff, Eino A. Aapro
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Publication number: 20090008076Abstract: A technique for climate control of, for example, base station circuitry within an enclosure involves placing base station circuitry within the enclosure and controlling the climate therein. A system according to this technique includes an enclosure suitable for use outside in a wide range of extreme weather conditions. A controller may, for example, control a fan tray with a heater to pull ambient air through a filtration unit, through the fan tray where the air is heated, and through cold start recirculation dampers.Type: ApplicationFiled: November 29, 2005Publication date: January 8, 2009Applicant: SANMINA-SCI CORPORATIONInventors: Zia Shariff, Andrew Hudz, Anthony Cormick Sharp
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Publication number: 20080301934Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.Type: ApplicationFiled: August 12, 2008Publication date: December 11, 2008Applicant: SANMINA SCI CORPORATIONInventor: George Dudnikov, JR.
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Publication number: 20080296057Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.Type: ApplicationFiled: August 12, 2008Publication date: December 4, 2008Applicant: SANMINA SCI CORPORATIONInventor: George Dudnikov, JR.
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Patent number: 7457132Abstract: Vias are used in multilayer printed circuit boards to route electrical interconnects between layers. Some via constructions embodiments result in the formation of a via-stub section. Via stub sections can distort signals passing through the interconnect and decrease the usable bandwidth of the interconnect. To minimize distortion and increase bandwidth, one or more terminating elements can be attached to the unterminated end of the via-stub section. The impedance terminating element may include, by way of non-limiting example, one or more resistors, capacitors, and/or inductors between the via stub and a ground layer. The impedance terminating element may be formed internally to the PCB or mounted to the PCB surface.Type: GrantFiled: October 20, 2005Date of Patent: November 25, 2008Assignee: Sanmina-SCI CorporationInventors: Franz Gisin, Christopher Herrick
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Publication number: 20080216298Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.Type: ApplicationFiled: March 10, 2008Publication date: September 11, 2008Applicant: SANMINA-SCI CORPORATIONInventor: George Dudnikov
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Publication number: 20080217049Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.Type: ApplicationFiled: March 10, 2008Publication date: September 11, 2008Applicant: SANMINA-SCI CORPORATIONInventor: George Dudnikov
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Patent number: 7394170Abstract: A backplane system for reconfigurable backplane power distribution includes circuit board slots, power entry modules, power distribution circuitry, and switching circuitry. The power distribution circuitry includes a first power configuration and a second power configuration and distributes the power from the power entry modules to at least one circuit board plugged into one of the circuit board slots. The switching circuitry switches between the first power configuration and the second power configuration to provide extended power capabilities.Type: GrantFiled: April 19, 2005Date of Patent: July 1, 2008Assignee: Sanmina-SCI CorporationInventor: Barry Kirkorian
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Patent number: 7345247Abstract: A circuit board threadplate for connection of a component to a circuit board is provided wherein such threadplate may be mechanically mounted to a circuit board without the use of manual labor. Specifically, the threadplate is compatible with present Surface Mount Technology robotic placement machines. Such circuit board threadplate includes a hollow substantially cylindrical member forming an extruded neck having an elongated section and a substantially flat surface at a first end of the elongated section and a flange extending from a second end of the elongated section. The flange provides a substantially flat surface suitable for soldering onto a surface of a circuit board. Additionally, the threadplate includes a cylindrical cavity positioned inside the substantially cylindrical member, extending in a direction aligned with the substantially cylindrical member. The cylindrical cavity may have a thread pattern suitable for receiving a screw-type fastener.Type: GrantFiled: October 4, 2002Date of Patent: March 18, 2008Assignee: Sanmina-SCI CorporationInventor: John A. Ireland
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Patent number: 7342713Abstract: Wavelength converter and methods are based on cross-gain modulation. The wavelength converter has two semiconductor optical amplifiers to perform double cross-gain modulations and double inversions. The first semiconductor optical amplifier performs a first cross-gain modulation on a first continuous wave light using the input light as a modulating light to generate an inverted first-stage cross-gain modulated light. The second semiconductor optical amplifier performs a second cross-gain modulation on a second continuous wave light using the first-stage cross-gain modulated light as a modulating light to generate a double-inverted output light. The output light is non-inverted with respect to the input light.Type: GrantFiled: January 7, 2005Date of Patent: March 11, 2008Assignee: Sanmina-SCI CorporationInventor: Brian Chaput
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Publication number: 20080056962Abstract: A compact module capable of performing one or more laboratory tests in nano-scale and/or micro-scale structures is provided. Such compact module may be made on silicon substrates by using manufacturing techniques typically applied to electronic and/or semiconductor manufacturing/fabrication. One aspect of the invention applies curling film technology to create and link three-dimensional elements that allow miniaturization of laboratory components and functions.Type: ApplicationFiled: November 29, 2006Publication date: March 6, 2008Applicant: SANMINA-SCI CORP.Inventor: Paul J. Mulqueen
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Publication number: 20070294890Abstract: A printed circuit board with improved signal integrity for one or more differential signal pairs incorporates one or more conductive regions. In an exemplary embodiment, via structures for the differential pair that interconnect signal traces are isolated from the conductive region by an antipad area around the via structures and a conductive bridge. In alternate embodiment, an antipad area around the via structures includes a bridge between the via structures. The antipad area may comprise, by way of non-limiting example, a clipped circular aperture or a modified rectangular aperture. The bridge may, by non-limiting examples, comprise a portion of the conductive region to permit impedance tailoring of the differential pair with respect to the conductive region.Type: ApplicationFiled: June 28, 2007Publication date: December 27, 2007Applicant: Sanmina-SCI CorporationInventors: Franz Gisin, Greg Schroeder