Abstract: A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.
Type:
Grant
Filed:
September 16, 2020
Date of Patent:
January 25, 2022
Assignee:
Seagate Technology LLC
Inventors:
Ivana Djurdjevic, Ara Patapoutian, Deepak Sridhara, Bengt Anders Ulriksson, Jeffrey John Pream
Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.
Abstract: Various implementations of network devices disclosed herein provide a method routing a data packet in an optical domain, the data packet including a first component or header and second component or routing information, stripping the first component or header from the data packet using a silicon photonic component, processing the first component or header in an electrical domain, and communicating the data packet without the first component or header to an optical delay line.
Abstract: A system including an analog block and a digital block. The analog block and the digital block are arranged on a package. The package includes a first ground coupled to the analog block and a second ground coupled to the digital block. The second ground is physically separate from the first ground. The package also includes a noise-mitigation stitching connector that has a first end connected to the first ground and a second end connected to the second ground.
Abstract: Carriers may be adapted, or configured, to allow devices received thereby to move towards and away from an interface end region. When devices are positioned proximate the interface end region of the carriers, interfaces of the devices may be presented by the carriers for operable coupling to an enclosure. When devices are positioned away from the interface end region of the carriers, interface adapters may be coupled to the interfaces of the devices, which may present a different interface for operable coupling to an enclosure.
Abstract: A recording head includes a channel waveguide that delivers light to a media-facing surface. A near-field transducer (NFT) is at an end of the channel waveguide and proximate to the media-facing surface. A laser including an active region has a longitudinal axis corresponding to a propagation direction of the channel waveguide. The active region includes a back facet and a front facet proximate the NFT. The front facet has a surface shape configured to suppress back reflection of the light.
Type:
Grant
Filed:
October 28, 2020
Date of Patent:
January 18, 2022
Assignee:
Seagate Technology LLC
Inventors:
Aidan Dominic Goggin, John Moloney, Reyad Mehfuz, Chuan Zhong, Christopher Neil Harvey
Abstract: A method of imaging surface features with a large (non-microscopic) field-of-view includes projecting a structured illumination pattern onto the transparent target. The surface features modify the structured illumination pattern, and an image of the modified structured illumination pattern is imaged at each of multiple different introduced phase shifts via an imaging device. The method further provides for extracting, from each of the captured phase-shifted images, image components that correspond to frequencies exceeding a cutoff frequency of the imaging device; and using the extracted image components to construct a corrected image of the surface features of the transparent target. The corrected image has a resolution that is greater than a spatially incoherent point-to-point optical resolution of the imaging device.
Abstract: Systems and methods are disclosed for a multiple detector data channel and data detection utilizing different cost functions. For example, a digital data channel system can have multiple data detectors where each data detector implements a distinct cost function for detecting data. A cost function analyzer can then selectively choose decisions from the multiple data detectors to generate a data sequence. In some examples, a dual detector system may have one detector implement a Soft-Output Viterbi Algorithm (SOVA) cost function and another detector implement a peak detection algorithm. Further, in some embodiments, the cost function analyzer can implement multiple selection criteria to determine which decisions to include in a data sequence from the multiple data detectors.
Abstract: A data storage device includes at least one data storage medium having a plurality of tracks. The data storage device also includes at least one actuator that supports at least one head that is configured to interact with different tracks of the plurality of tracks on the at least one data storage medium to service commands from a host. The data storage device further includes a seek control circuit communicatively coupled to the at least one actuator. The seek control circuit is configured to store the commands from the host in at least one queue for execution by the at least one actuator. The seek control module is also configured to adjust power provided to the at least one actuator for seek operations to the different tracks of the plurality of tracks based on command age-related measurements of the commands from the host.
Type:
Grant
Filed:
October 20, 2020
Date of Patent:
January 11, 2022
Assignee:
SEAGATE TECHNOLOGY LLC
Inventors:
Josiah Natan Wernow, Raye A. Sosseh, Colin Graham Presly, Mark A. Gaertner
Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.
Type:
Grant
Filed:
May 31, 2017
Date of Patent:
January 11, 2022
Assignee:
Seagate Technology LLC
Inventors:
Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
Abstract: An apparatus includes a recording head for reading and writing data on a data storage medium. The recording head includes a reader having a first media-confronting surface. The recording head also includes a main write pole having a second media-confronting surface that protrudes in front of the first media-confronting surface.
Type:
Grant
Filed:
October 15, 2020
Date of Patent:
January 11, 2022
Assignee:
SEAGATE TECHNOLOGY LLC
Inventors:
Lihong Zhang, Xiong Liu, Swee Chuan Gan
Abstract: A background operation is internally triggered by firmware of a disk drive. During a training phase defined by a first time period, access latency of host commands is monitored during rotational position sorting command selection. During a sorting phase after the training phase, a sorting threshold is defined based on the access latencies measured during the training phase. The background command is selected for execution in the sorting phase if the seek and rotational latency is less than the sorting threshold.
Type:
Grant
Filed:
April 22, 2020
Date of Patent:
January 11, 2022
Assignee:
Seagate Technology, LLC
Inventors:
Abhay T. Kataria, LingZhi Yang, Jonathan H. Ormsby
Abstract: A method includes accessing a first top level entry of a first table of the base volume, the first top level entry having at least a first bottom level entry. The method also includes receiving a first request for a metadata snapshot of the base volume, including the first bottom level entry. The method also includes generating a second top level entry of the first table, the second top level entry configured to point to the at least first bottom level entry of the first table, and the second top level entry configured to operate as a first snapshot of the first table including the at least first bottom level entry.
Abstract: A recording head has a waveguide that delivers optical energy from an energy source and a write pole extending to a media-facing surface of the recording head. The recording head also has a near-field transducer coupled to receive the optical energy from the waveguide and emit surface plasmons from the media-facing surface towards a recording medium while the write pole applies a magnetic field to the recording medium. The near-field transducer has an extended portion that, as-manufactured, protrudes beyond the media-facing surface by a first distance.
Type:
Grant
Filed:
December 30, 2020
Date of Patent:
January 11, 2022
Assignee:
Seagate Technology LLC
Inventors:
Michael A. Seigler, Peng Zhang, David James Ellison, James D. Kiely, Edwin F. Rejda
Abstract: Systems and methods presented herein provide a controller that is operable to monitor a plurality of background commands to a storage device over a pre-determined period of time and to determine how often each of the background commands is issued during the pre-determined period of time. The controller is further operable to establish a time interval for each of the background commands, and to issue each of the background commands at their respective time intervals.
Abstract: A multi-port data storage device to at least provide port-to-port communication between nodes. The multi-port storage device includes a first port, a second port and a bridge. The first port can be operatively coupled to a first node of a plurality of nodes. The second port can be operatively coupled to a second node of the plurality of nodes. The bridge can receive one or more data packets via the first or second ports to be transmitted to one of the plurality of nodes and to transmit one or more received data packets to another multi-port data storage device, to the first node, or to the second node.
Abstract: Systems and methods are disclosed for improving data channel design by applying transform domain analytics to more reliably extract user data from a signal. In certain embodiments, an apparatus may comprise a channel circuit configured to receive an analog signal at an input of the channel circuit, and sample the analog signal to obtain a set of signal samples. The channel circuit may further apply a filter configured to perform transform domain analysis to the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and having a higher signal to noise ratio (SNR) than the set of signal samples. The channel circuit may detect first bit transform domain representation values from the first subset, and determine channel bit values encoded in the analog signal based on the set of signal samples and using the first bit transform domain representation values detected from the first subset as side information.
Abstract: A recording head includes one or more transducer elements, and an electrically insulative layer encasing the one or more transducer elements. The recording head also includes a substrate below the electrically insulative layer. The recording head further includes a heat sinking layer between the electrically insulative layer and the substrate.
Type:
Grant
Filed:
December 9, 2020
Date of Patent:
January 4, 2022
Assignee:
SEAGATE TECHNOLOGY LLC
Inventors:
Helene Parwana Habibi, Vasudevan Ramaswamy, Raul H. Andruet, Neil Zuckerman, Frank A. McGinnity, Giovanni A. Badini Confalioneri, Martin L. McGarry, James G. Wessel, Pablo G. Levi