Abstract: Apparatuses, systems, and methods are disclosed related to heat assisted magnetic recording. According to one embodiment, an apparatus that includes a heat sink region and a near field transducer region is disclosed. The near field transducer region is thermally coupled to the heat sink region. At least one of the heat sink region and the near field transducer region includes both an inner core and an outer shell. The inner core can be comprised of a non-plasmonic material and the outer shell can be comprised of a plasmonic material. In further embodiments, the inner core is comprised of a material having a relatively higher electron-phonon coupling constant and the outer shell is comprised of a material having a relatively lower electron-phonon coupling constant.
Type:
Application
Filed:
May 23, 2014
Publication date:
December 25, 2014
Applicant:
Seagate Technology LLC
Inventors:
Tong Zhao, John C. Duda, Michael Christopher Kautzky
Abstract: A device includes a magnet and a magnetizer. The magnetizer is operable to rotate with respect to the magnet. The rotation generates an acoustic pure tone at a particular frequency. A combination of the magnet and the magnetizer has a magnetic profile. The combination is altered to superimpose a particular harmonic shape on the magnetic profile to reduce the acoustic pure tone at the particular frequency.
Abstract: A memory controller receives memory access requests from a host terminal, the memory access requests from the host terminal including one or both of host read requests and host write requests. The memory controller generates memory access requests. Priorities are assigned to the memory access requests. The memory access requests are segregated to memory unit queues of at least one set of memory unit queues, the set of memory unit queues associated with a memory unit. Each memory access request is sent to the memory unit according to a priority and an assigned memory unit queue of the memory access request.
Abstract: A magnetoresistive data writer and reader may be generally configured at least with a magnetoresistive (MR) element contacting a magnetic shield that is constructed of (Ni78Fe22)99.8O0.2 material. The magnetic shield may be formed with an electrodeposition process that uses ?-diketones derivatives to form nano-crystalline grain structure after a subsequent annealing at temperatures above 400° C.
Type:
Grant
Filed:
March 12, 2013
Date of Patent:
December 23, 2014
Assignee:
Seagate Technology LLC
Inventors:
Jie Gong, Ibro Tabakovic, Steve Riemer, Michael Christopher Kautzky
Abstract: The embodiments disclose a continuous thin film magnetic layer and a patterned hard mask layer configured to be deposited onto the continuous thin film magnetic layer and to have plural ion implantations, wherein the ion implantations are configured to create chemically and structurally altered localized magnetic regions unprotected by the patterned hard mask layer.
Abstract: Multiple signals are read, respectively, from multiple different cross-track positions of a track of a magnetic medium. Weighting coefficients for each of the multiple signals are determined. The weighting coefficients are applied to the respective signals to form weighted signals. The weighted signals are combined and the combined signal is used to recover data stored in the track.
Abstract: An apparatus includes a near field transduce (NFT), a waveguide core, and a dielectric resonator. The waveguide core is configured to propagate electromagnetic radiation. The dielectric resonator is disposed between the waveguide core and the NFT and is configured to transfer energy of the electromagnetic radiation to the NFT.
Abstract: In general, this disclosure relates to various techniques for detecting corrupt bits in a data stream. The techniques may allow a data storage device to detect corrupt bits prior to transformation of the data stream and subsequent to transformation of the data stream. A data storage device may include a first error-related code generating unit configured to generate a first error-related code based on received data and combine the first error-related code and the received data to generate a first data stream. The data storage device may further include a transform unit configured to transform the first data stream to a transformed data stream. The data storage device may also include a second error-related code generating unit configured to generate a second error-related code based on the transformed data stream.
Abstract: An apparatus comprising a memory configured to store data and a controller. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller is configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether the read is successful, (iii) if the read is not successful, perform a plurality of reads with a varying value of the threshold voltage, (iv) read a calibration value from a look-up table based on the plurality of reads and (v) set the threshold value in response to the calibration value.
Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) read data from a region of a memory circuit during a read scrub of the region and (ii) generate a plurality of statistics based on (a) the data and (b) one or more bit flips performed during an error correction of the data. The memory circuit is generally configured to store the data in a nonvolatile condition. One or more reference voltages may be used to read the data. The second circuit may be configured to (i) update a plurality of parameters of the region based on the statistics and (ii) compute updated values of the reference voltages based on the parameters.
Abstract: The embodiments disclose a block copolymer assembly structure, including a first pattern and second pattern with a first density of patterned features integrated in data and servo zones, a silicon substrate with thin film layers deposited thereon and patterned using the first density of first pattern and second pattern features and a template fabrication pattern with a second density greater than the first density created using ordered block copolymer periodic structures across a portion of the substrate.
Type:
Grant
Filed:
October 5, 2012
Date of Patent:
December 16, 2014
Assignee:
Seagate Technology LLC
Inventors:
XiaoMin Yang, Kim Yang Lee, HongYing Wang
Abstract: Apparatus for retracting and extending sets of operational processing devices in a multi-device enclosure. In accordance with some embodiments, an enclosed housing is provided with opposing first and second ends. Sleds are individually movable between a retracted position within the enclosed housing and an extended position in which the sled projects from the first end. Each sled supports a group of processing devices. A control board is disposed within the enclosed housing adjacent the second end. A plurality of flex circuits contactingly engage the processing devices to provide communication paths between the processing devices and the control board in both the retracted and extended positions of the sleds.
Type:
Application
Filed:
November 11, 2013
Publication date:
December 11, 2014
Applicant:
Seagate Technology LLC
Inventors:
Anthony John Pronozuk, Shawn Jacob Noland, James Edward Dykes, William Leon Rugg, Chau Chin Low
Abstract: Apparatus and method for performing secure erasure of a processing device, such as a data storage device in an object storage system. In accordance with some embodiments, an apparatus is provided with a plurality of processing devices arranged within an enclosed housing and each having an associated memory. A mechanical switch is coupled to the enclosed housing. The associated memories of the processing devices are securely erased responsive to activation of the mechanical switch.
Type:
Application
Filed:
November 11, 2013
Publication date:
December 11, 2014
Applicant:
Seagate Technology LLC
Inventors:
Anthony John Pronozuk, Shawn Jacob Noland, James Edward Dykes, William Leon Rugg
Abstract: Apparatus and method for maintaining processing devices at a nominally common temperature, such as but not limited to storage devices in a multi-device networked storage enclosure. In accordance with some embodiments, an enclosed housing has a first side adjacent a cold zone with a lower ambient temperature and an opposing second side adjacent a warm zone with a higher ambient temperature. First and second processing devices are arranged within the enclosed housing so that the first processing device is adjacent the cold zone and the second processing device is adjacent the warm zone. First and second thermal interface material (TIM) modules are contactingly affixed to the first and second devices and are provided with different heat conductivities so that the first and second devices are maintained at a nominally common operational temperature.
Type:
Application
Filed:
November 11, 2013
Publication date:
December 11, 2014
Applicant:
Seagate Technology LLC
Inventors:
Anthony John Pronozuk, Shawn Jacob Noland, James Edward Dykes, William Leon Rugg
Abstract: Method and apparatus for securely erasing data from a non-volatile memory, such as but not limited to a flash memory array. In accordance with various embodiments, an extended data set to be sanitized from the memory is identified. The extended data set includes multiple copies of data having a common logical address and different physical addresses within the memory. The extended data set is sanitized in relation to a characterization of the data set. The data sanitizing operation results in the extended data set being purged from the memory and other previously stored data in the memory being retained.
Type:
Grant
Filed:
April 29, 2011
Date of Patent:
December 9, 2014
Assignee:
Seagate Technology LLC
Inventors:
Ryan James Goss, David Scott Seekins, Jonathan W. Haines, Timothy R. Feldman
Abstract: Devices and/or methods may decode failed data, e.g., utilizing side information related to the failed data to determine how to decode the failed data. The side information may include, e.g., a decoding-success score representing an estimated amount of errors within a failed data portion, a remaining amount of unread portions of a data block including failed data, an amount of requested portions of a data block including failed data, if the failed data is buffered, and a decoding status of any previously-failed data.
Abstract: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure.
Type:
Grant
Filed:
March 4, 2013
Date of Patent:
December 9, 2014
Assignee:
Seagate Technology LLC
Inventors:
Dimitar V. Dimitrov, Olle Gunnar Heinonen, Dexin Wang, Haiwen Xi
Abstract: A data storage system may be configured with at least a data storage device that has a controller connected to at least a first data writing transducer and a second data writing transducer. The controller may be adapted to set different first and second healing thresholds for the respective data writing transducers in response to passive data track testing.
Abstract: Digital rights management (DRM) can be implemented through use of an anchor point based digital rights management system. In one embodiment, a device may comprise an anchor point circuit including a memory and a processor. The processor may be configured to receive a title key from a digital content provider, the title key used to encrypt a digital property to produce an encrypted digital property. The processor may be further configured to generate a binding key, encrypt the title key with the binding key to produce a title pre-key, and store the binding key in the memory. In another embodiment a system may comprise an interface configured to communicate with a content provider, and an anchor point circuit configured to bind a digital property received from the content provider to the anchor point circuit such that the digital property can only be used in conjunction with the anchor point circuit.