Abstract: Three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select devices may be implemented to provide a high voltage and a low voltage to specific bit lines, while a middle voltage may also be provided. In a particular embodiment, the select devices comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs).
Type:
Grant
Filed:
July 13, 2009
Date of Patent:
August 20, 2013
Assignee:
Seagate Technology LLC
Inventors:
Chulmin Jung, Jinyoung Kim, Yong Lu, Harry Liu
Abstract: A magnetic tunnel junction includes an amorphous ferromagnetic reference layer having a first reference layer side and an opposing second reference layer side. The first reference layer side has a greater concentration of boron than the second reference layer side. A magnesium oxide tunnel barrier layer is disposed on the second side of the amorphous ferromagnetic reference layer. The magnesium oxide tunnel barrier layer has a crystal structure. An amorphous ferromagnetic free layer is disposed on the magnesium oxide tunnel barrier layer.
Type:
Grant
Filed:
September 13, 2012
Date of Patent:
August 20, 2013
Assignee:
Seagate Technology LLC
Inventors:
Xilin Peng, Konstantin Nikolaev, Taras Pokhil, Victor Sapazhnikov, Yonghua Chen
Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
Type:
Grant
Filed:
September 12, 2012
Date of Patent:
August 20, 2013
Assignee:
Seagate Technology LLC
Inventors:
Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
Abstract: A slider may have a first surface on an air bearing surface (ABS) and a laser recess formed in a second surface of the slider, opposite the first surface. A laser can then be positioned in the laser recess with the laser extending from the slider to a top plane. A stud may be formed adjacent to and separated from the laser on the second surface of the slider with the stud extending from the second surface of the slider to the top plane.
Type:
Grant
Filed:
July 29, 2011
Date of Patent:
August 20, 2013
Assignee:
Seagate Technology LLC
Inventors:
Yongjun Zhao, Mike Allen Seigler, Mark Henry Ostrowski
Abstract: A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate, a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, an emitter contact layer disposed in a second side of the semiconductor substrate, and a base layer separating the plurality of collector contacts from the emitter contact layer. Each collector contact is electrically isolated from each other. A resistive sense memory cells is electrically coupled to each collector contacts and a bit line. The base layer and the emitter contact layer provide an electrical path for the plurality of collector contacts.
Abstract: A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.
Type:
Grant
Filed:
October 21, 2011
Date of Patent:
August 13, 2013
Assignee:
Seagate Technology LLC
Inventors:
Chulmin Jung, Maroun Georges Khoury, Yong Lu, Young Pil Kim
Abstract: A magnetic tunnel junction having a compsensation element is disclosed. The magnetic tunnel junction includes a reference element, and a compensation element having an opposite magnetization moment to a magnetization moment of the reference element. A free magnetic layer is between the reference element and the compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic layer from the reference element. The free magnetic layer includes Co100-X-YFeXBY wherein X is a value being greater than 30 and Y is a value being greater than 15.
Abstract: A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer.
Type:
Grant
Filed:
November 16, 2010
Date of Patent:
August 13, 2013
Assignee:
Seagate Technology LLC
Inventors:
Insik Jin, Xiaobin Wang, Yong Lu, Haiwen Xi
Abstract: A magnetic stack includes multiple granular layers, at least one of the multiple granular layers is a magnetic layer that includes exchange coupled magnetic grains separated by a segregant having Ms greater than 100 emu/cc. Each of the multiple granular layers have anisotropic thermal conductivity.
Type:
Grant
Filed:
June 30, 2011
Date of Patent:
August 13, 2013
Assignee:
Seagate Technology LLC
Inventors:
Yingguo Peng, Jan-Ulrich Thiele, Ganping Ju, Thomas Patrick Nolan, Yinfeng Ding, Alexander Qihong Wu
Abstract: Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.
Type:
Grant
Filed:
May 23, 2012
Date of Patent:
August 13, 2013
Assignee:
Seagate Technology LLC
Inventors:
Maroun Georges Khoury, Hongyue Liu, Brian Lee, Andrew John Gjevre Carter
Abstract: A waveguide extends away from a media-facing surface. The waveguide includes top and bottom cladding layers and a core disposed therebetween. The core includes a middle core layer and an outside core layer having respective first and second indices of refraction. The first index of refraction is smaller than the second index of refraction. A near field transducer is disposed within the middle core layer proximate the media-facing surface.
Abstract: A spin-transfer torque memory unit includes a free magnetic layer having a magnetic easy axis; a reference magnetic element having a magnetization orientation that is pinned in a reference direction; an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the magnetic reference element; and a compensation element adjacent to the free magnetic layer. The compensation element applies a bias field on the magnetization orientation of the free magnetic layer. The bias field is formed of a first vector component parallel to the easy axis of the free magnetic layer and a second vector component orthogonal to the easy axis of the free magnetic layer. The bias field reduces a write current magnitude required to switch the direction of the magnetization orientation of the free magnetic layer.
Abstract: In order to improve a consistent data track during writing to a storage medium, a plurality of read sensors are affixed to a transducer head. In one implementation, the transducer head includes multiple read sensors placed up-track of the write pole. In another implementation, the transducer head includes at least one read sensor placed up-track of the write pole and at least one read sensor placed down-track of the write pole. Each position of the multiple read sensors relative to the write pole may be unique. One or more read signals of selected read sensors are used to determine the read location and therefore the write pole location relative to the storage medium.
Abstract: In an example, a method of manufacturing a transducer head comprises configuring a control circuit to actively synchronize magnetic responses of a shield and a write pole during operation. The method also comprises configuring the control circuit to energize at least one coil wire during operation with a current direction opposite to current flow in a main transducer head coil. In another example, a method comprises actively synchronizing magnetic responses of a shield and a write pole. In another example, a transducer head comprises a write pole and a shield, and a control circuit actively synchronizes magnetic responses of the shield and the write pole.
Type:
Application
Filed:
February 3, 2012
Publication date:
August 8, 2013
Applicant:
Seagate Technology LLC
Inventors:
Radek Lopusnik, Mourad Benakli, Kirill Aleksandrovich Rivkin, Declan Macken, James Gary Wessel, Jason Bryce Gadbois
Abstract: A method includes activating a stress-effecting layer of a thin film structure, having the stress effecting layer adjacent to a magnetic layer, to induce a magneto-elastic anisotropy in the magnetic layer.
Type:
Grant
Filed:
January 18, 2012
Date of Patent:
August 6, 2013
Assignee:
Seagate Technology LLC
Inventors:
Yiao-Tee Hsia, Wei Peng, Timothy J. Klemmer
Abstract: An apparatus and associated method for gaging the repeatability of a tool is provided by a pivot assembly. The pivot assembly has a pivot member with a tool engagement feature to selectively receive a torque from the tool at a pivot axis. The pivot assembly also has a first magnetically permeable member fixed in movement with the pivot member. The pivot assembly further has a second magnetically permeable member. An abutment member abuttingly engages the pivot member to limit its pivotal travel at a position where the first and second magnetically permeable members are magnetically coupled together, without contacting each other for being separated by a gap, by a magnetic force of attraction urging the pivot member toward the second magnetically permeable member.
Type:
Grant
Filed:
May 19, 2010
Date of Patent:
August 6, 2013
Assignee:
Seagate Technology LLC
Inventors:
Michael William Pfeiffer, Brendan Joseph Moore
Abstract: A perpendicular magnetic recording medium adapted for high recording density and high data recording rate comprises a non-magnetic substrate having at least one surface with a layer stack formed thereon, the layer stack including a perpendicular recording layer containing a plurality of columnar-shaped magnetic grains extending perpendicularly to the substrate surface for a length, with a first end distal the surface and a second end proximal the surface, wherein each of the magnetic grains has: (1) a gradient of perpendicular magnetic anisotropy field Hk extending along its length between the first end and second ends; and (2) predetermined local exchange coupling strengths along the length.
Type:
Grant
Filed:
October 11, 2011
Date of Patent:
August 6, 2013
Assignee:
Seagate Technology LLC
Inventors:
Shaoping Li, Kaizhong Gao, Lei Wang, Wenzhong Zhu, Xiaobin Wang
Abstract: Power is routed from one or more power supplies. As consistent with one or more example embodiments, a data storage device senses and/or is informed of the availability and voltage level of one or more power supplies. Based upon the availability and voltage level of power supplies, circuits in the memory device are powered using one or more of the sensed power supplies. In some applications, the power is drawn in a manner that emulates the behavior of one or more circuits that are respectively powered.
Type:
Grant
Filed:
June 26, 2009
Date of Patent:
August 6, 2013
Assignee:
Seagate Technology LLC
Inventors:
Jon David Trantham, Christopher Thomas Cole
Abstract: Various embodiments of the present invention are generally directed to a magnetically responsive lamination that may be constructed with a spacer layer disposed between a first and second ferromagnetic free layer. At least one ferromagnetic free layer can have a coupling sub-layer that enhances magnetoresistance ratio (MR) of the magnetically responsive lamination.
Type:
Grant
Filed:
September 21, 2011
Date of Patent:
August 6, 2013
Assignee:
Seagate Technology LLC
Inventors:
Mark William Covington, Qing He, Wonjoon Jung, Vladyslav Alexandrovich Vas'ko
Abstract: A method of producing a slider wafer populated with electromagnetic components optically aligned with photonic elements for HAMR applications. Laser chips are transferred from a laser substrate wafer to the slider wafer by a massively parallel printing transfer process. After wafer bonding the laser chips to the slider wafer, the shape and optical alignment of the photonic elements are precisely aligned en masse by lithographic processing.
Type:
Grant
Filed:
March 31, 2010
Date of Patent:
August 6, 2013
Assignee:
Seagate Technology LLC
Inventors:
Marcus B. Mooney, Mark Anthony Gubbins, Bredan Lafferty, Alin Mihai Fecioru