Bipolar select device for resistive sense memory

- Seagate Technology LLC

A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate, a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, an emitter contact layer disposed in a second side of the semiconductor substrate, and a base layer separating the plurality of collector contacts from the emitter contact layer. Each collector contact is electrically isolated from each other. A resistive sense memory cells is electrically coupled to each collector contacts and a bit line. The base layer and the emitter contact layer provide an electrical path for the plurality of collector contacts.

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Description
CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of Ser. No. 12/498,661, filed Jul. 7, 2009, now U.S. Pat. No. 8,159,856, the contents of which is hereby incorporated by reference in its entirety.

BACKGROUND

Fast growth of the pervasive computing and handheld/communication industry has generated exploding demand for high capacity nonvolatile solid-state data storage devices. Current technology like flash memory has several drawbacks such as slow access speed, limited endurance, and the integration difficulty. Flash memory (NAND or NOR) also faces significant scaling problems.

Resistive sense memories are promising candidates for future nonvolatile and universal memory by storing data bits as either a high or low resistance state. One such memory, MRAM, features non-volatility, fast writing/reading speed, almost unlimited programming endurance and zero standby power. The basic component of MRAM is a magnetic tunneling junction (MTJ). MRAM switches the MTJ resistance by using a current induced magnetic field to switch the magnetization of MTJ. As the MTJ size shrinks, the switching magnetic field amplitude increases and the switching variation becomes more severe. Resistive RAM (RRAM) is another resistive sense memory that has a variable resistance layer that can switch between a high resistance state and a low resistance state (for example by the presence or absence of a conductive filament) by applicant of a current or voltage.

However, some yield-limiting factors must be overcome before resistive sense memory enters the production stage. One challenge is that the resistive sense memory element often requires a large current in order for writing to occur. In particular, spin torque RAM (STRAM) requires high currents at fast write speeds. MOSFET select transistors have been used in such resistive sense memories. However, the area required by the MOSFET to achieve the currents needed is large. There is a need for select devices having reduced area requirements at specified writing currents for resistive sense memories.

BRIEF SUMMARY

The present disclosure relates to a bipolar select device for resistive sense memory. In particular, the present disclosure relates to a resistive sense memory apparatus that includes a bipolar select transistor that has high drive current capability for its size. The bipolar select transistor consumes a small area and shares one contact across multiple memory cells.

One illustrative resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate, a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, an emitter contact layer disposed in a second side of the semiconductor substrate, and a base layer separating the plurality of collector contacts from the emitter contact layer. Each collector contact is electrically isolated from each other. A resistive sense memory cells is electrically coupled to each collector contacts and a bit line. The base layer and the emitter contact layer provide an electrical path for the plurality of collector contacts.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be more completely understood in consideration of the following detailed description of various embodiments of the disclosure in connection with the accompanying drawings, in which:

FIG. 1 is a cross-sectional schematic diagram of an illustrative magnetic tunnel junction data cell;

FIG. 2 is a top view schematic diagram of an illustrative resistive sense memory array;

FIG. 3 is a cross-sectional schematic diagram of the illustrative resistive sense memory apparatus of FIG. 2 taken along line 3-3;

FIG. 4 is a cross-sectional schematic diagram of the illustrative resistive sense memory apparatus of FIG. 2 taken along line 4-4; and

FIG. 5 is a flow diagram of an illustrative method of writing to a memory unit array.

The figures are not necessarily to scale. Like numbers used in the figures refer to like components. However, it will be understood that the use of a number to refer to a component in a given figure is not intended to limit the component in another figure labeled with the same number.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying set of drawings that form a part hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense. The definitions provided herein are to facilitate understanding of certain terms used frequently herein and are not meant to limit the scope of the present disclosure.

Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by those skilled in the art utilizing the teachings disclosed herein.

The recitation of numerical ranges by endpoints includes all numbers subsumed within that range (e.g. 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.80, 4, and 5) and any range within that range.

As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” encompass embodiments having plural referents, unless the content clearly dictates otherwise. As used in this specification and the appended claims, the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.

The present disclosure relates to a bipolar select device for resistive sense memory. In particular, the present disclosure relates to a resistive sense memory apparatus that includes a bipolar select transistor that has high drive current capability for its size. The bipolar select transistor consumes a small area and shares one contact across multiple memory cells, thus the number of electrical contacts is reduced. While the present disclosure is not so limited, an appreciation of various aspects of the disclosure will be gained through a discussion of the examples provided below.

Variable resistive memory includes memory cells that switch between at least a low resistance data state and a high resistance data state by passing a write current through the resistive memory cell (i.e., resistive RAM or RRAM). In some embodiments the resistive memory cell is a phase change data cell (i.e., PCRAM) or a programmable metallization data cell (i.e., PMCRAM). In some embodiments the resistive memory is a magnetic tunnel junction such as, for example, a spin transfer torque memory cell (i.e., STRAM). These magnetic tunnel junction data cells are further described below. Semiconductor fabrication techniques can be utilized to form the resistive sense memory apparatus and arrays described herein. The terms “emitter” and “collector” are interchangeable depending on the direction current is flowing through the resistive sense memory apparatus and arrays described herein.

The resistive sense memory apparatus described herein allows bipolar electrical conduction through the device at bulk conduction transport rates, allowing higher current flow per area than conventional semiconductor transistor select devices. Thus, the area required for each resistive sense memory apparatus can be reduced and the density of the memory array is increased, as compared to conventional memory array devices. Thus the select devices described herein can be termed as either NPN or PNP devices. An NPN device can have a deep Pwell for isolation purposes and a PNP device can have a deep Nwell for isolation purposes. In either case, an oxide region can work for isolation purposes.

FIG. 1 is a cross-sectional schematic diagram of an illustrative magnetic tunnel junction data cell 10. The magnetic tunnel junction data cell 10 includes a ferromagnetic free layer 12 and a ferromagnetic reference (i.e., pinned) layer 14. The ferromagnetic free layer 12 and a ferromagnetic reference layer 14 are separated by an oxide barrier layer 13 or tunnel barrier. A first electrode 15 is in electrical contact with the ferromagnetic free layer 12 and a second electrode 16 is in electrical contact with the ferromagnetic reference layer 14. The ferromagnetic layers 12, 14 may be made of any useful ferromagnetic (FM) alloys such as, for example, Fe, Co, Ni and the insulating barrier layer 13 may be made of an electrically insulating material such as, for example an oxide material (e.g., Al2O3 or MgO). Other suitable materials may also be used.

The electrodes 15, 16 electrically connect the ferromagnetic layers 12, 14 to a control circuit providing read and write currents through the ferromagnetic layers 12, 14. The resistance across the magnetic tunnel junction data cell 10 is determined by the relative orientation of the magnetization vectors or magnetization orientations of the ferromagnetic layers 12, 14. The magnetization direction of the ferromagnetic reference layer 14 is pinned in a predetermined direction while the magnetization direction of the ferromagnetic free layer 12 is free to rotate under the influence of a spin torque. Pinning of the ferromagnetic reference layer 14 may be achieved through, e.g., the use of exchange bias with an antiferromagnetically ordered material such as PtMn, IrMn and others. When the magnetization orientation of the ferromagnetic free layer 12 is parallel and in the same direction of the magnetization orientation of the ferromagnetic reference layer 14 the magnetic tunnel junction is described as being in the low resistance state or “0” data state. When the magnetization orientation of the ferromagnetic free layer 12 is anti-parallel and in the opposite direction of the magnetization orientation of the ferromagnetic reference layer 14 the magnetic tunnel junction is described as being in the high resistance state or “1” data state.

Switching the resistance state and hence the data state of the magnetic tunnel junction data cell 10 via spin-transfer occurs when a current, passing through a magnetic layer of the magnetic tunnel junction data cell 10, becomes spin polarized and imparts a spin torque on the free layer 12 of the magnetic tunnel junction data cell 10. When a sufficient spin torque is applied to the free layer 12, the magnetization orientation of the free layer 12 can be switched between two opposite directions and accordingly the magnetic tunnel junction data cell 10 can be switched between the parallel state (i.e., low resistance state or “0” data state) and anti-parallel state (i.e., high resistance state or “1” data state) depending on the direction of the current.

The illustrative spin-transfer torque magnetic tunnel junction data cell 10 may be used to construct a memory device that includes multiple magnetic tunnel junction data cells in an array where a data bit is stored in magnetic tunnel junction data cell by changing the relative magnetization state of the free magnetic layer 12 with respect to the pinned magnetic layer 14. The stored data bit can be read out by measuring the resistance of the cell which changes with the magnetization direction of the free layer relative to the pinned magnetic layer. In order for the spin-transfer torque magnetic tunnel junction data cell 10 to have the characteristics of a non-volatile random access memory, the free layer exhibits thermal stability against random fluctuations so that the orientation of the free layer is changed only when it is controlled to make such a change.

FIG. 2 is a top view schematic diagram of an illustrative resistive sense memory array 20. The resistive sense memory array 20 shown includes three resistive sense memory apparatus or devices 30, 40 and 50 arranged as a plurality of rows and separated by deep trench isolation elements 35, 45, 55, and 65. The deep trench isolation elements 35, 45, 55, and 65 can be any useful electrically isolating element such as an oxide material, for example. The deep trench isolation elements 35, 45, 55, and 65 electrically isolate the resistive sense memory apparatus or devices 30, 40 and 50 from each other.

Each resistive sense memory apparatus or devices 30, 40 and 50 include a bipolar select device that is electrically coupled to a plurality of resistive sense memory cells. The bipolar select device includes a semiconductor substrate 32, 42, and 52 and a plurality of collector contacts 34, 44, and 54. Each collector contact 34, 44, and 54 is disposed on a first side or major surface of the semiconductor substrate and is electrically coupled to a resistive sense memory cell, as described below. Each collector contact 34, 44, and 54 is electrically isolated from each other with an isolation element 36, 46, and 56. The isolation element 36, 46, and 56 can be any useful electrically isolating element such as an oxide material, for example.

Each resistive sense memory apparatus or devices 30, 40 and 50 include an emitter contact 33, 43, and 53. The illustrated emitter contact 33, 43, and 53 extends through the first side or major surface of the resistive sense memory apparatus or devices 30, 40 and 50 and is electrically coupled to a source line. The illustrated emitter contact 33, 43, and 53 extends through the first side or major surface of the resistive sense memory apparatus or devices 30, 40 and 50 and is electrically coupled to an emitter contact layer (described below).

Each resistive sense memory apparatus or devices 30, 40 and 50 include a base contact 31, 41, and 51. The illustrated base contact 31, 41, and 51 extends through the first side or major surface of the resistive sense memory apparatus or devices 30, 40 and 50 and is electrically coupled to a word line. The illustrated base contact 31, 41, and 51 extends through the first side or major surface of the resistive sense memory apparatus or devices 30, 40 and 50 and is electrically coupled to a base layer (described below). In some embodiments, the emitter contact 33, 43, and 53 and the base contact 31, 41, and 51 are disposed adjacent to each other or on a same side of the resistive sense memory apparatus or devices 30, 40 and 50.

Each resistive sense memory apparatus or devices 30, 40 and 50 can be described as a three contact device. One word line and one source line provide an electrical path to a plurality of resistive sense memory cells by selecting the desired bit line electrically couple to the resistive sense memory cells.

FIG. 3 is a cross-sectional schematic diagram of the illustrative resistive sense memory apparatus of FIG. 2 taken along line 3-3. While the figures illustrate three resistive sense memory apparatus or devices each having three resistive sense memory cells, it is understood that the resistive sense memory array can include any useful number of resistive sense memory apparatus each having any useful number of resistive sense memory cells.

The illustrative resistive sense memory apparatus 30 includes three collector contacts 34. Each collector contact 34 is electrically isolated from each other with an isolation element 36, as described above, and are disposed in a first side of the of the semiconductor substrate 32 (an upper or top side of FIG. 3). An emitter contact layer 37 is disposed in a second side of the semiconductor substrate 32 (a lower or bottom side of FIG. 3) the emitter contact layer 37 is electrically coupled to the emitter contact 33 that extends through the first side of the of the semiconductor substrate 32. The second side opposes the first side.

A base layer 38 separates the plurality of collector contacts 34 from the emitter contact layer 37. The base layer 38 is electrically coupled to the base contact 31 that extends through the of the base contact region 39 in the first side of the semiconductor substrate 32. A resistive sense memory cell 1011, 1012, 1013 is electrically coupled to one of the plurality of collector contacts 34 and a bit line BL11, BL12, BL13. The base layer 38 and the emitter contact layer 37 provide an electrical path for the plurality of collector contacts 34. The base layer 38 is electrically coupled to a word line WL1 through the base contact region 39. The base contact region or layer 39 is made of a similar semiconductor material type as the base layer 38 except for it having a higher level of doping. The emitter contact layer 37 is electrically coupled to a source line SL1. One word line WL1 and one source line SL1 provide an electrical path to a plurality of resistive sense memory cells 1011, 1012, 1013 by selecting the desired bit line BL11, BL12, BL13 that is electrically coupled to the resistive sense memory cell. Thus, the number of contacts required to construct the resistive sense memory apparatus is reduced.

FIG. 4 is a cross-sectional schematic diagram of the illustrative resistive sense memory apparatus of FIG. 2 taken along line 4-4. The illustrative resistive sense memory array includes three resistive sense memory apparatus 30, 40 and 50. One collector contact 34, 44 and 54 is shown for each resistive sense memory apparatus 30, 40 and 50.

Each collector contact 34, 44 and 54 is electrically isolated from each other with an isolation element 45 and 55, as described above, and are disposed in a first side of the of the semiconductor substrate (an upper or top side of FIG. 4). An emitter contact layer 37, 47, and 57 is disposed in a second side of the semiconductor substrate (a lower or bottom side of FIG. 4) the emitter contact layer 37, 47 and 57 is electrically coupled to the emitter contact that extends through the first side of the of the semiconductor substrate. The second side opposes the first side. A base layer 38, 48 and 58 separates the plurality of collector contacts 34, 44 and 54 from the emitter contact layer 37, 47 and 57. The base layer 38. 48 and 58 is electrically coupled to the base contact that extends through the first side of the of the semiconductor substrate.

A resistive sense memory cell 1011, 1021, 1031 is electrically coupled to one of the plurality of collector contacts 34, 44, and 54 and a bit line BL11, BL21, BL31. The base layer 38, 48 and 58 and the emitter contact layer 37, 47 and 57 provide an electrical path for the plurality of collector contacts 34, 44, and 54. The base layer 38, 48 and 58 is electrically coupled to a word line and the emitter contact layer 37, 47 and 57 is electrically coupled to a word line. One word line and one source line provide an electrical path to a plurality of resistive sense memory cells 1011, 1021, 1031 selecting the desired bit line BL11, BL21, BL31 that is electrically coupled to the resistive sense memory cell. Thus, the number of contacts required to construct the resistive sense memory apparatus is reduced.

The collector contacts 34, 44 and 54 and the emitter contact layer 37, 47 and 57 has the same conductivity type and the base layer 38, 48 and 58 and base contact region 39 has an opposing conductivity type. In many embodiments, the collector contacts 34, 44 and 54 and the emitter contact layer 37, 47 and 57 have N type conductivity and the base layer 38, 48 and 58 has P type conductivity. In other embodiments, the collector contacts 34, 44 and 54 and the emitter contact layer 37, 47 and 57 have P type conductivity and the base layer 38, 48 and 58 has N type conductivity.

FIG. 5 is a flow diagram of an illustrative method of writing to a memory unit array 100. The method includes providing a bipolar resistive sense memory (RSM) apparatus as described above at block 101. Then the method includes writing a first data state (i.e., low resistance state) to a plurality of resistive sense memory cells by applying a forward bias across an emitter contact layer of a bipolar select device and selected bit lines electrically coupled to the plurality of resistive sense memory cells to be written to at block 102 or writing a second data state (i.e., high resistance state) to a plurality of resistive sense memory cells by applying a reverse bias across an emitter contact layer of a bipolar select device and selected bit lines electrically coupled to the plurality of resistive sense memory cells to be written to at block 103. The forward bias condition places one or more resistive sense memory cells in the low resistance state at block 104 and reverse bias condition places one or more resistive sense memory cells in the high resistance state at block 105.

Thus, embodiments of the BIPOLAR SELECT DEVICE FOR RESISTIVE SENSE MEMORY are disclosed. The implementations described above and other implementations are within the scope of the following claims. One skilled in the art will appreciate that the present disclosure can be practiced with embodiments other than those disclosed. The disclosed embodiments are presented for purposes of illustration and not limitation, and the present invention is limited only by the claims that follow.

Claims

1. A spin transfer torque memory apparatus comprising:

a bipolar select device comprising: a semiconductor substrate having a first side and an opposing second side; a plurality of collector contacts disposed in the first side of the of the semiconductor substrate, wherein each collector contact is electrically isolated from each other; an emitter contact layer disposed in the second side of the semiconductor substrate, the emitter contact layer being electrically coupled to a source line; and a base layer disposed between the plurality of collector contacts and the emitter contact layer, the base layer being electrically coupled to a word line; and
a plurality of spin transfer torque memory cells, wherein one of the plurality of spin transfer torque memory cells is electrically coupled to one of the plurality of collector contacts and a bit line associated with the one of the plurality of spin transfer torque memory cells, wherein the base layer and the emitter contact layer provides an electrical path for the plurality of collector contacts.

2. A spin transfer torque memory apparatus according to claim 1, wherein the collector contacts and the emitter contact layer have N type conductivity and the base layer has P type conductivity.

3. A spin transfer torque memory apparatus according to claim 1, wherein the collector contacts and the emitter contact layer have P type conductivity and the base layer has N type conductivity.

4. A spin transfer torque memory apparatus according to claim 1, wherein the spin transfer torque memory cells comprise magnetic tunnel junctions switchable between a high resistance data state and a low resistance data state by spin torque transfer of a polarized current through the magnetic tunnel junction.

5. A spin transfer torque memory apparatus according to claim 1, wherein the word line and the source line provide an electrical path to the plurality of spin transfer torque memory cells by selecting a desired bit line.

6. A spin transfer torque memory apparatus according to claim 1, further comprising a plurality of bipolar select devices, wherein each bipolar select device forms a row of a memory array.

7. A spin transfer torque memory apparatus according to claim 6, wherein each bipolar select device is electrically isolated from each other.

8. A spin transfer torque memory apparatus according to claim 6, wherein each bipolar select device is electrically isolated from each other by deep trench isolation.

9. A spin transfer torque memory apparatus according to claim 1, wherein the emitter contact layer extends along a length of the bipolar select device and the plurality of collector contacts are disposed along the length of the bipolar select device.

10. A spin transfer torque memory array, comprising:

a plurality of bipolar select devices, each bipolar select device forming a row of a memory array, each bipolar select device comprising: a semiconductor substrate; a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, wherein each collector contact is electrically isolated from each other; an emitter contact layer disposed in a second side of the semiconductor substrate, the second side opposing the first side, the emitter contact layer being electrically coupled to a source line; and a base layer separating the plurality of collector contacts from the emitter contact layer, the base layer being electrically coupled to a word line; and
a plurality of spin transfer torque memory cells, wherein one of the plurality of spin transfer torque memory cells is electrically coupled to one of the plurality of collector contacts and a bit line associated with the one of the plurality of spin transfer torque memory cells, wherein the base layer of each bipolar select device and the emitter contact layer of each bipolar select device provides an electrical path for the plurality of collector contacts for the bipolar select device.

11. A spin transfer torque memory array according to claim 10, wherein each bipolar select device is electrically isolated from each other.

12. A spin transfer torque memory array according to claim 10, wherein each bipolar select device is electrically isolated from each other by deep trench isolation.

13. A spin transfer torque memory array according to claim 10, wherein the emitter contact layer extends along a length of the bipolar select device and the plurality of collector contacts are disposed along the length of the bipolar select device.

14. A spin transfer torque memory array according to claim 10, wherein the collector contacts and the emitter contact layer have N type conductivity and the base layer has P type conductivity.

15. A spin transfer torque memory array according to claim 10, wherein the collector contacts and the emitter contact layer have P type conductivity and the base layer has N type conductivity.

16. A spin transfer torque memory array according to claim 10, wherein the spin transfer torque memory cells comprise magnetic tunnel junctions switchable between a high resistance data state and a low resistance data state by spin torque transfer of a polarized current through the magnetic tunnel junction.

17. A spin transfer torque memory array according to claim 10, wherein the word line and the source line provide an electrical path to the plurality of spin transfer torque memory cells by selecting a desired bit line.

18. A method, comprising:

writing a first data state to a plurality of spin transfer torque memory cells by applying a forward bias across an emitter contact layer of a bipolar select device and selected bit lines electrically coupled to the plurality of spin transfer torque memory cells to be written to, wherein the bipolar select device comprises: a semiconductor substrate; a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, wherein each collector contact is electrically isolated from each other and each collector is electrically coupled to a spin transfer torque memory cell; the emitter contact layer disposed in a second side of the semiconductor substrate, the second side opposing the first side, the emitter contact layer being electrically coupled to a source line; and a base layer separating the plurality of collector contacts from the emitter contact, the base layer being electrically coupled to a word line.

19. A method according to claim 18, further comprising writing a second data state to a plurality of spin transfer torque memory cells by applying a reverse bias across an emitter contact layer of a bipolar select device and selected bit lines electrically coupled to the plurality of spin transfer torque memory cells to be written to.

20. A method according to claim 18, wherein the writing step comprises applying a spin polarized current thought the spin transfer torque memory cells.

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Patent History
Patent number: 8514608
Type: Grant
Filed: Mar 16, 2012
Date of Patent: Aug 20, 2013
Patent Publication Number: 20120175718
Assignee: Seagate Technology LLC (Cupertino, CA)
Inventor: Maroun Georges Khoury (Burnsville, MN)
Primary Examiner: Toan Le
Assistant Examiner: Hai Pham
Application Number: 13/422,219