Patents Assigned to Seagate Technologies
  • Patent number: 9466329
    Abstract: Methods for determining a variable data frequency for recording data on a zone of a magnetic storage disc, each zone including a plurality of tracks and each track including a plurality of sectors, the method includes measuring a signal to noise ratio (S/N) around at least a first track in a first zone; and modulating a data frequency based on the measured S/N around the first track.
    Type: Grant
    Filed: September 12, 2015
    Date of Patent: October 11, 2016
    Assignee: Seagate Technology LLC
    Inventors: Richard P. Michel, Ray V. Rigles, Tong Shirh Stone
  • Patent number: 9468126
    Abstract: Apparatus for retracting and extending sets of operational processing devices in a multi-device enclosure. In accordance with some embodiments, an enclosed housing is provided with opposing first and second ends. Sleds are individually movable between a retracted position within the enclosed housing and an extended position in which the sled projects from the first end. Each sled supports a group of processing devices. A control board is disposed within the enclosed housing adjacent the second end. A plurality of flex circuits contactingly engage the processing devices to provide communication paths between the processing devices and the control board in both the retracted and extended positions of the sleds.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: October 11, 2016
    Assignee: Seagate Technology LLC
    Inventors: Anthony John Pronozuk, Shawn Jacob Noland, James Edward Dykes, William Leon Rugg, Chau Chin Low
  • Patent number: 9466324
    Abstract: A method is disclosed that includes forming at least one substrate alignment mark and at least one lithography alignment mark in a substrate; forming a seed layer on the substrate; and forming a guide pattern and at least one guide pattern alignment mark in the seed layer, where the at least one guide pattern alignment mark is formed over the at least one substrate alignment mark. The method further includes determining an alignment error of the at least one guide pattern alignment mark relative to the at least one substrate alignment mark; and patterning features on at least one region of the substrate, where the features are positioned on the substrate based on the at least one lithography alignment mark and the alignment error.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: October 11, 2016
    Assignee: Seagate Technology LLC
    Inventors: HongYing Wang, Kim Y Lee, Yautzong Hsu, Nobuo Kurataka, Gennady Gauzner, Shuaigang Xiao
  • Patent number: 9468116
    Abstract: An apparatus and associated methodology contemplating an enclosure configured to securely contain a circuit board. The enclosure has a cover defining a flange operably extending substantially parallel to the circuit board in direct contact with the circuit board. The enclosure also has a body extending from the flange that is operably separated from the circuit board. A connecting member has opposing planar sides operably pressing to contain the flange against the circuit board in supporting the circuit board within the enclosure.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: October 11, 2016
    Assignee: Seagate Technology LLC
    Inventor: William G. Voss
  • Patent number: 9465555
    Abstract: A method for improving I/O performance by a storage controller is provided. The method includes receiving a command completion from a storage device and checking for a command stored in a command queue for more than a predetermined time period. If a command has been in the command queue for more than the predetermined time period, then issuing the command and removing the command from the command queue. If no commands have been stored in the command queue for more than the predetermined time period, then determining if there are any uncompleted commands previously issued to the storage device. If there are not any uncompleted commands previously issued to the storage device, then processing a next command in the command queue and removing the next command from the command queue.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: October 11, 2016
    Assignee: Seagate Technology LLC
    Inventors: Michael David Barrell, Zachary David Traut
  • Patent number: 9466325
    Abstract: Provided herein are apparatuses and methods related to creating a patterned resist layer on a substrate; selectively treating at least a resist-contacting layer of the substrate in contact with the patterned resist layer to create a patterned growth guiding mechanism and growing patterned magnetic features guided by the patterned growth guiding mechanism.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: October 11, 2016
    Assignee: Seagate Technology LLC
    Inventors: Thomas P. Nolan, Kim Y. Lee, Shuaigang Xiao, Tom Chang, Yingguo Peng
  • Patent number: 9465745
    Abstract: Apparatus and associated method concerning managing access commands with a main storage space, a volatile buffer, and a nonvolatile buffer. The volatile buffer is configured to store a plurality of command nodes that are associated with data access commands received from a remote device and directed to the main storage space. The apparatus also has command prioritizing logic configured for using a prescribed rule in repeatedly identifying two or more candidate command nodes of the plurality that are at least individually favored for execution with respect to the main storage space, for selecting one of the candidate command nodes for the execution, and for transferring a nonselected one of the candidate command nodes from the volatile buffer to the nonvolatile buffer where the nonselected command node continues to be considered for execution with respect to the main storage space but is no longer considered by the prescribed rule when identifying subsequent candidate command nodes in the volatile buffer.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: October 11, 2016
    Assignee: Seagate Technology, LLC
    Inventor: Satish Laxmanrao Rege
  • Patent number: 9466327
    Abstract: Apparatus and method for supporting a data recording medium adjacent a spindle motor hub. In some embodiments, an annular disc spacer has a plurality of nominal dimensions and is formed of a glass material and at least one additive to provide the disc spacer with a selected color. The color of the disc spacer is selected responsive to at least one of the plurality of nominal dimension of the disc spacer. The color may have a wavelength in the human detectable range of from about 350 nanometers, nm to about 700 nm.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: October 11, 2016
    Assignee: Seagate Technology LLC
    Inventor: Mark A. Toffle
  • Patent number: 9467288
    Abstract: Techniques for encryption key destruction for secure data erasure via an external interface or physical key removal are described. Electrical destruction of key material retained in a memory of a storage device renders the device securely erased, even when the device is otherwise inoperable. The memory (e.g. non-volatile, such as flash) stores key material for encrypting/decrypting storage data for the device. An eraser provides power and commands to the memory, even when all or any portion of the device is inoperable. The commands (e.g. erase or write) enable zeroizing or destroying the key material, rendering data encrypted with the destroyed key material inaccessible, and therefore securely erased. Alternatively, the memory is a removable component (e.g. an external security device or smartcard) coupled to the device during storage operation. Removing and physically destroying the memory renders the device securely erased. The device and/or the memory are sealed to enable tamper detection.
    Type: Grant
    Filed: January 17, 2015
    Date of Patent: October 11, 2016
    Assignee: Seagate Technology LLC
    Inventors: Dmitry Obukhov, Bin Tan
  • Patent number: 9461904
    Abstract: Examples of selective enablement of operating modes or features of a storage system via host transfer rate detection are disclosed. In one example implementation according to aspects of the present disclosure, a storage device includes an interface configured to couple the storage device to a computing host indirectly via an intermediate fabric; and a storage controller configured to determine whether a nominal data transfer rate of the interface across the intermediate fabric is at or above a predetermined threshold, and selectively enable coalescing of status information that is to be returned to the computing host via status combining across multiple host requests responsive to it being determined that the nominal data transfer rate is at or above the predetermined threshold.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 4, 2016
    Assignee: Seagate Technology LLC
    Inventor: Andrew John Tomlin
  • Patent number: 9460751
    Abstract: Systems and methods are disclosed for binding shingled recording bands in data storage devices, particularly devices employing shingled magnetic recording. In one embodiment, an apparatus may comprise a controller configured to define boundaries of an area of a data storage medium based on a constraint and a list of defective sectors. In another embodiment, an apparatus may comprise a data storage device including a memory configured to store data in a shingled manner where one track partially overlaps an adjacent track, and a controller configured to define boundaries of a plurality of bands, each band including a plurality of tracks of the memory, based on the results of an error discovery scan for defective sectors of the memory.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: October 4, 2016
    Assignee: Seagate Technology LLC
    Inventor: Timothy R Feldman
  • Patent number: 9458936
    Abstract: Certain exemplary aspects of the present disclosure are directed towards an apparatus in which a base deck and a base deck cover interface with one another to provide a permeability path. The base deck includes an outer region, and the base deck cover includes a lip that interfaces with the outer region of the base deck to provide the permeability path. The permeability is further defined by at least three interleaved sidewalls of the base deck and base deck cover that define two segments of the permeability path. The permeability path is filled with a polymer material that creates a seal between the base deck and base deck cover.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: October 4, 2016
    Assignee: Seagate Technology LLC
    Inventors: Frank William Bernett, Neal Gunderson, Steven Lee Weber
  • Patent number: 9460747
    Abstract: A method for nano-patterning includes imprinting features in a resist with an imprint mold to form one or more topographic surface patterns on the imprinted resist. A block copolymer (“BCP”) material is deposited on the imprinted resist, wherein a molecular dimension L0 of the BCP material correlates by an integer multiple to a spacing dimension of the one or more topographic surface patterns on the imprinted resist. The deposited BCP is annealed and at least a portion of the annealed BCP is removed, forming a template having discrete domains.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: October 4, 2016
    Assignee: Seagate Technology LLC
    Inventors: Yuan Xu, Kim Y. Lee, David S. Kuo, Koichi Wago, Wei Hu
  • Patent number: 9460756
    Abstract: Certain exemplary aspects of the present disclosure are directed towards an apparatus in which a base deck and a cover are coupled to one another via a coupling that forms a hermetic seal around a cavity defined by the base deck and the cover. A guard protects the coupling from external forces via a surface aligned with and extending along the coupling.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: October 4, 2016
    Assignee: Seagate Technology LLC
    Inventors: Kent J. Forbord, Andrew J. Hutchinson, Steven L. Weber
  • Patent number: 9454319
    Abstract: The present disclosure relates to examples of data hardening. In one example according to aspects of the present disclosure, a method comprises receiving, at a storage device, power loss information in a first format associated with a first protocol. The method further comprises converting, at the storage device, the power loss information in the first format to a second format associated with a second protocol, wherein converting the power loss information in the first format to the second format comprises converting one of a power loss primitive or a power loss command to one of a primitive or command for hardening data.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: September 27, 2016
    Assignee: Seagate Technology LLC
    Inventor: Ross John Stenfort
  • Patent number: 9456515
    Abstract: A rackmountable storage enclosure includes a chassis. The chassis includes one or more power supplies and a plurality of drawers, each extendable through a front surface of the chassis. Each drawer of the plurality of drawers provides mounting for one or more storage devices. All storage devices in any drawer of the plurality of drawers are inserted or removed through a common side of the drawer. Any storage device may be inserted or removed from any drawer of the plurality of drawers even if the side surfaces of the chassis are each parallel to and in contact with a wall, each of the walls extending forward at least to a fully extended length of any drawer. Electrical failures in any one drawer are prevented from affecting any other drawer of the plurality of drawers. The one or more power supplies provides DC power to the plurality of drawers.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: September 27, 2016
    Assignee: Seagate Technology LLC
    Inventors: Victor Key Pecone, Kevin James Lonergan, Brenden Michael Rust, George Alexander Kalwitz
  • Patent number: 9455004
    Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: September 27, 2016
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S. Alhussien, Yunxiang Wu, Sundararajan Sankaranarayanan, Zhengang Chen, Erich F. Haratsch
  • Patent number: 9449630
    Abstract: A slider that includes a leading edge surface; a trailing edge surface; and an air bearing surface (ABS) positioned between the leading edge surface and the trailing edge surface, wherein the trailing edge surface includes a read-write element, at least one low surface energy region and at least one high surface energy region.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: September 20, 2016
    Assignee: Seagate Technology LLC
    Inventors: Ajaykumar Rajasekharan, Gary J. Kunkel, David J. Ellison, Narayanan Ramakrishnan
  • Patent number: 9450619
    Abstract: A method for system for dynamic channel Log Likelihood Ratio (LLR) quantization for a Solid State Drive (SSD) controller is a targeted approach to scaling which results in a scaled, quantized set of LLRs whose relative magnitude remains undisturbed from an original magnitude. The method reads a set of voltages from each channel of the SSD. The set of reads is configured in location and number for performance. Once a set is returned, the method determines an LLR for each of the voltages read resulting in a raw set of LLRs. Targeted scaling results in a scaled set of LLRs between an upper limit and a lower limit determined for reading by a decoder. Once scaled, the LLRs are rounded and quantized for use by the decoder to produce an Error Correction Code (ECC).
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: September 20, 2016
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Erich F. Haratsch
  • Patent number: 9448882
    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, and estimating a voltage associated with the data in the data set corresponding to the critical location.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: September 20, 2016
    Assignee: Seagate Technology LLC
    Inventors: Haitao Xia, Fan Zhang, Shu Li, Jun Xiao