Abstract: A spread spectrum system having a self-oscillating delay-line digital pulse width modulator and a method for mitigating electromagnetic interference. The spread spectrum system has a pseudo-random pattern generator connected to a digital-to-analog converter, which in turn is connected to a linear regulator. The linear regulator receives a reference voltage from the digital-to-analog converter and creates a frequency varying voltage that serves as an input voltage for delay elements of a delay-line based digital pulse width modulator. In response to frequency varying input signal, the delay-line based digital pulse width modulator generates a frequency varying voltage that is input to a switching network to vary its switching frequency.
Abstract: A thyristor and a method for manufacturing the thyristor that includes a gate region extending from the first major surface into a semiconductor substrate and an anode region extending from the second major surface into the semiconductor substrate. A cathode region extends into a portion of the gate region. Optionally, enhanced doped regions extend into the gate and anode regions. A mesa structure having a height HG is formed from the first major surface and a mesa structure having a height HA is formed from the second major surface. The gate region extends under the first major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HG. The anode region extends under the second major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HA.
Abstract: In one embodiment, an electronic device package (1) includes a leadframe (2) with a flag (3). An electronic chip (8) is attached to the flag (3) with a die attach layer (9). A trench (16) having curved sidewalls is formed in the flag (3) in proximity to the electronic chip (8) and surrounds the periphery of the chip (8). An encapsulating layer (19) covers the chip (8), portions of the flag (3), and at least a portion of the curved trench (16). The curved trench (16) reduces the spread of die attach material across the flag (3) during chip attachment, which reduces chip and package cracking problems, and improves the adhesion of encapsulating layer (19). The shape of the curved trench (16) prevents flow of die attach material into the curved trench (16), which allows the encapsulating layer (19) to adhere to the surface of the curved trench (16).
Abstract: In one embodiment, a current sense circuit is formed with a pair of series connected switches that are used to steer a load current and form a current sense signal.
Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element.
Abstract: A circuit and a method for nullifying temperature dependence of a circuit characteristic. The circuit includes a plurality of transistors configured such that they generate a gate voltage that includes a threshold voltage as a component. The gate voltage is applied to a transistor to generate a current that is proportional to a process transconductance parameter. The current is applied to a comparator having a differential pair of transistors, wherein each transistor has a process transconductance parameter. The circuit takes the ratios of the process transconductance parameter associated with the current to that of each transistor of the differential pair. By rationing the process transconductance parameters, temperature dependence is nullified or negated. The ratios can be used to set the hysteresis voltage of the comparator.
Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.
Abstract: In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.
Abstract: In one embodiment, a power supply controller has a variable frequency oscillator that is used for controlling a PWM controller. The power supply controller varies a frequency of the variable frequency oscillator.
Abstract: A selected bandgap reference (11) of a voltage generator (10) is operated at a duty cycle that is less than one hundred percent. The seclectable bandgap reference (11) has at a high current consumption when enabled and a low current consumption when disabled. The output voltage of the selectable bandgap reference (11) is stored on a storage element (13) when the selectable bandgap reference (11) is enabled. A high impedance amplifier (16) receives the stored voltage and generates the reference voltage.
Abstract: In one embodiment, a charge compensation region is formed in a body of semiconductor material. A conductive layer is coupled to the charge compensation layer. In a further embodiment, the charge compensation region comprises a trench filled with opposite conductivity type semiconductor layers.
Abstract: In one embodiment, an output transistor and a bias compensation device are placed in proximity to each other on the same package substrate. The bias compensation device is electrically isolated but thermally coupled to the output transistor, and is configured to provide a output signal for adjusting bias to the output transistor.
Abstract: A Schottky diode capable of sustaining a breakdown voltage of greater than about 250 volts and a method for its manufacture. An epitaxial layer disposed on a semiconductor substrate has a thickness of at least about 15 micrometers and an impurity concentration ranging from about 1×1014 atoms per cubic centimeter to about 1×1015 atoms per cubic centimeter. A guard ring extends from about 3 micrometers to about 15 micrometers into the epitaxial layer. A dielectric material is formed over the epitaxial layer and a portion of the dielectric material is removed to expose a portion of the guard ring and a portion of the epitaxial layer within the guard ring. An electrically conductive material is formed over the exposed portion of the epitaxial layer and an electrically conductive material is formed in contact with a bottom surface of the semiconductor substrate.
Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a screening electrode spaced apart from a channel region.
Abstract: A lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches bounding in part a multiplicity of striped doped regions having opposite or alternating conductivity types.
Abstract: A semiconductor device (2) includes a semiconductor substrate (12) having a surface (13) formed with a first recessed region (20). A first dielectric material (60) is deposited in the first recessed region and formed with a second recessed region (76), and a second dielectric material (100) is grown over the first dielectric material to seal the second recessed region.
Abstract: A semiconductor device (50) includes a semiconductor die (20) having a first surface (14) for forming electronic circuitry. A coating layer (16) formed on a second surface (15) of the semiconductor die has a color that contrasts with the color of the semiconductor die. The coating layer is patterned to expose a portion of the second surface to reveal information pertaining to the semiconductor device. The coating layer is patterned by directing a radiation beam (30) such as a laser to selectively remove material from the coating layer.