Patents Assigned to Semiconductor Component Industries, L.L.C.
  • Method of forming a floating charge pump and structure therefor
    Patent number: 7259613
    Abstract: In one embodiment, a capacitor of a charge pump circuit is referenced to a high side voltage or top voltage rail.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: August 21, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Stephen Meek, Alan R. Ball
  • Diagnostic circuit and method therefor
    Patent number: 7256605
    Abstract: In one embodiment, a diagnostic circuit is used to test the on-resistance of a transistor.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: August 14, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Alan R. Ball
  • Semiconductor device having trench structures and method
    Patent number: 7256119
    Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: August 14, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Gordon M. Grivna, Peter J. Zdebel
  • Semiconductor device edge termination structure
    Patent number: 7253477
    Abstract: In one embodiment, an edge termination structure is formed in a semiconductor layer of a first conductivity type. The termination structure includes an isolation trench and a conductive layer in contact with the semiconductor layer. The semiconductor layer is formed over a semiconductor substrate of a second conductivity type. In a further embodiment, the isolation trench includes a plurality of shapes that comprise portions of the semiconductor layer.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: August 7, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Gary H. Loechelt, Peter J. Zdebel, Gordon M. Grivna
  • Semiconductor package and leadframe therefor having angled corners
    Patent number: 7247931
    Abstract: A leadframe for a semiconductor package is formed with an indentation on a bottom surface. A side of the indentation is used to form a mold-lock that assists in securing the leadframe to the encapsulation material of the semiconductor package.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: July 24, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Chuan Kiak Ng, Ein Sun Ng, Yeu Wen Lee
  • Power switch structure with low RDSon and low current limit and method
    Patent number: 7230299
    Abstract: In one embodiment, a power switch device (33) includes a first MOSFET device 41 and a second MOSFET device (42). A split gate structure (84) including a first gate electrode (48,87) controls the first MOSFET device (41). A second gate electrode (49,92) controls the second MOSFET device (42). A current limit device (38) is coupled to the first gate electrode (48,97) to turn on the first MOSFET device during a current limit mode. A comparator device (36) is coupled to the second gate electrode (49,92) to turn on the second MOSFET device (42) when the power switch device (33) is no longer in current limit mode.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: June 12, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Stephen P. Robb, David K. Briggs
  • Power system inhibit method and device and structure therefor
    Patent number: 7227203
    Abstract: A power control system (25) uses two separate currents to control a startup operation of the power control system (25). The two currents are shunted to ground to inhibit operation of the power control system (25) and one of the two currents is disabled to minimize power dissipation. The two independently controlled currents are generated by a multiple output current high voltage device (12) responsively to two separate control signals (23,24).
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: June 5, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Josef Halamik, Jefferson W. Hall
  • Semiconductor device with wire bond inductor and method
    Patent number: 7227240
    Abstract: A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L150) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: June 5, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: James Knapp, Francis Carney, Harold Anderson, Yenting Wen, Cang Ngo
  • Delay circuit and method therefor
    Patent number: 7218174
    Abstract: In one embodiment, a delay circuit is formed to use cascode coupled transistors to receive signals from a differential pair and increase the propagation through the delay circuit.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: May 15, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Ira E. Baskett
  • LDMOS transistor with enhanced termination region for high breakdown voltage with on-resistance
    Patent number: 7208385
    Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: April 24, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Zia Hossain, Mohamed Imam, Joe Fulton
  • Semiconductor component and method of manufacturing
    Patent number: 7205605
    Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: April 17, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Peyman Hadizad, Jina Shumate, Ali Salih
  • Thyristor and method of manufacture
    Patent number: 7205583
    Abstract: A thyristor and a method for manufacturing the thyristor that includes providing a semiconductor substrate that has first and second major surfaces. A first doped region is formed in the semiconductor substrate, wherein the first doped extends from the first major surface into the semiconductor substrate. The first doped region has a vertical boundary that has a notched portion. A second doped region is formed in first doped region, wherein the second doped region extends from the first major surface into the first doped region. A third doped region is formed in the semiconductor substrate, wherein the third doped region extends from the second major surface into the semiconductor substrate.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: April 17, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Emmanuel Saucedo-Flores
  • Multi-chip semiconductor connector and method
    Patent number: 7202106
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 10, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • Multi-chip semiconductor connector assembly method
    Patent number: 7202105
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 10, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • Interface system and method therefor
    Patent number: 7196549
    Abstract: In one embodiment, a differential transistor pair of an ECL differential amplifier is formed on two different semiconductor die.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: March 27, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Ira E. Baskett
  • Method of forming a low capacitance semiconductor device and structure therefor
    Patent number: 7192814
    Abstract: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: March 20, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Prasad Venkatraman
  • Semiconductor diode and method therefor
    Patent number: 7189610
    Abstract: In one embodiment, a diode is formed with anodes on two surfaces of a semiconductor substrate.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: March 13, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: John David Moran, Blanca Estela Kruse, Jose Rogelio Moreno
  • Semiconductor device having reduced gate charge and reduced on resistance and method
    Patent number: 7189608
    Abstract: In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body region. A gate layer is disposed over the semiconductor material and has a first opening over the JFET region and a second opening over the body region.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: March 13, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Prasad Venkatraman, Irene S. Wan
  • Lead-free integrated circuit package structure
    Patent number: 7180170
    Abstract: An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: February 20, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Phillip C. Celaya, James S. Donley, Stephen C. St. Germain
  • Method of forming a self-gated transistor and structure therefor
    Patent number: 7157959
    Abstract: In one embodiment, a self-gated transistor includes a sensing portion that generates a sense signal that is used to drive the self-gated transistor.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: January 2, 2007
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Alan R. Ball, Paul J. Harriman, Stephen Meek, Suzanne Nee