Abstract: A semiconductor device is formed to have a shape that reduces the thermal resistance of the semiconductor device.

Abstract: In one embodiment, a pair of differential amplifiers have outputs coupled together. A signal received on one input results in signals coupled to the outputs that substantially cancel each other at the outputs.

Abstract: A seconductor device (50) includes a semiconductor die (20) having a first surface (14) for forming electronic circuitry. A coating layer (16) formed on a second surface (15) of the semiconductor die has a color that contrasts with the color of the semiconductor die. The coating layer is patterned to expose a portion of the second surface to reveal information pertaining to the semiconductor device. The coating layer is patterned by directing a radiation beam (30) such as a laser to selectively remove material from the coating layer.

Abstract: A receiver circuit (12) includes a first gate (24) that receives an input signal (VIN0, VIN1) and has an output (32, 34) for providing an output signal (VG0, VG1). A shifting circuit (20) is coupled for shifting the common mode potential of the input signal to produce a shifted signal (VSH0, VSH1). A second gate (22) has an input (27, 28) that receives the shifted signal and an output coupled to the output of the first gate.

Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84,85,87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.

Abstract: In one embodiment, an ECL logic device uses a capacitor to couple a positive voltage to an output and reduce the rise time of the output signal.

Abstract: In one embodiment, a power MOSFET driver uses two different voltages for the operating voltage of the two output drivers of the power MOSFET driver.

Abstract: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.

Abstract: A power factor correction (PFC) circuit (10) includes a pulse width modulator (31) operating in response to a clock signal (CLK) for switching a coil current (ICOIL) over a charging period (TCHG) to correct a power factor at a node (32). The coil current discharges over a discharging period (TDSCHG) to develop an output voltage (VOUT) at an output (30). An oscillator (35) generates the clock signal to have a clock period (TCLK) longer than the sum of the charging and discharging periods, thereby operating in a discontinuous mode, and has an input (39) for sensing the input signal to modify the clock period.

Abstract: In one embodiment, a differential amplifier uses a diode coupled transistor and a series resistor to set a Voh output level and uses another transistor in parallel with the diode coupled transistor and resistor to set a Vol output level.

Abstract: A method of forming a leadframe and a semiconductor package using the leadframe facilitates selectively forming leads for the package. The leadframe is formed with a first portion of the leads extending from a panel of the leadframe into a molding cavity section of the leadframe. After encapsultaion, a portion of the leadframe panel is used to form a second portion of the leads that is external to the package body.

Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: A semiconductor package (101) has a die (1), a leadframe (4), a bond pad (6), an encapsulation (3) and a wire bond ball (2). The wire bond ball is formed on the bond pad by bonding one end of a bond wire (7), and remainder of the bond wire is removed. Locations (23) for attaching the wire bond ball are recorded with reference to fiducials (5) on the lead frame. The encapsulation covers the die, deposits and die attach flag (24) of the lead frame. The wire bond ball is exposed where the encapsulation is removed. The locations for making openings (17) for exposing the wire bond ball is determined by recorded coordinates when the wire bond ball is formed. Exposed wire bond ball is plated, forming a lead to electrically connect to the die.

Abstract: In one embodiment, a concentric ring ESD structure includes a first p-type region and a second p-type region are formed in a layer of semiconductor material. The two p-type regions are coupled together with a floating n-type buried layer. The first and second p-type regions form a back-to-back diode structure with the floating n-type buried layer. A pair of shorted n-type and p-type contact regions is formed in each of the first and second regions. An isolation region is formed between the first and second p-type regions.

Abstract: An inrush current limiter circuit (20) includes a detection circuit (30) that produces a control signal (VDRIVE) from a sense current (ISENSE). A power transistor responds to the control signal and has a source (51) coupled to an input node (12) to receive a supply voltage (ground) and a drain (53) for routing a load current (ILOAD) to an output node (45) as a protection signal (VSW). A sense transistor responds to the control signal and has a source scaled to the source of the power transistor and coupled to the input node to route a portion of the load current to the output node as the sense current.

Abstract: In one embodiment, a matrix of free-standing semiconductor shapes are oxidized to form a low capacitance isolation tub. The adjacent rows of shapes in the matrix are offset with respect to each to minimize air gap and void formation during tub formation. In a further embodiment, the spacing between adjacent rows is less than the spacing between shapes within a row.

Abstract: In one embodiment, a power supply controller is configured to amplify a feedback signal and a voltage reference signal by gains that are substantially constant over an operating frequency of the power supply controller.

Abstract: A transistor (10) is formed in a semiconductor substrate (12) whose top surface (48) is formed with a pedestal structure (24). A conductive material (40) is disposed along a side surface (28) of the pedestal structure to self-align an edge of a first conduction electrode (45) of the transistor. A dielectric spacer (55) is formed along a side surface (49) of the conductive material to self-align a contact area (56) of the first conduction electrode.

Abstract: In one embodiment, a dc/dc converter network (71) is described. The converter network (71) includes at least one GaAs depletion mode or normally on FET device (711, 712). The converter network (71) is a two-port system having a positive input terminal (710), a positive output terminal (730), and a negative input terminal (720) connected to a negative output terminal (740). A first GaAs depletion mode FET (711) is connected between the positive input terminal (710) and an internal node (795). A second GaAs depletion mode FET (712) is connected between the internal node (795) and the common negative terminals (720, 740). A control circuit (780) is connected gate leads of the two FETs (711, 712), to alternatively switch the devices from a current conducting mode to a current blocking mode. An inductor (760) is connected between the internal node (795) and the positive output terminal (730). The GaAs depletion mode devices provide a converter network with improved performance.

Abstract: In one embodiment, a capacitor of a charge pump circuit is referenced to a high side voltage or top voltage rail.