Abstract: An imaging device may include an image sensor that generates frames of image data in response to incident light with an array of image pixels, and processing circuitry that processes the image data. The processing circuitry may include a transformation circuit that applies transforms to subsampled frames of image data that are generated using a subset of the image pixels to produce transform values, and a comparator circuit that compares the transform values. The processing circuitry may determine that motion has occurred between sequential frames if a difference between a first transform value corresponding to a first image frame and a second transform value corresponding to a second image frame exceeds a threshold value. In response to determining that motion has occurred, the image sensor may generate full-frame image data using all of the pixels of the array of image pixels.

Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side and an active area on the second side of the die. The semiconductor packages may also include two or more bumps coupled to two or more die pads on a second side of the die. The semiconductor packages may include an optically transmissive lid coupled to the semiconductor die through an adhesive, two or more bumps, and a first redistribution layer (RDL). The semiconductor package may include a second redistribution layer (RDL) coupled with the first RDL on the second side of the semiconductor die. The second RDL may extend to the first side of the semiconductor die. The first RDL may extend to an edge of the semiconductor die.

Abstract: Implementations of a semiconductor device may include a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and a temporary die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The thickness may be between 0.1 microns and 125 microns. The warpage of the semiconductor die may be less than 200 microns.

Abstract: Implementations of a method of separating a semiconductor substrate from a boule including a semiconductor material may include creating a damage layer in a first end of a boule including semiconductor material; heating the boule; and cooling the boule to separate one or more semiconductor substrates from the boule at the damage layer.

Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.

Abstract: An illustrative wearable hearing device or hearing aid includes: a speaker that converts a reproduced signal into reproduced audio; a microphone that converts ambient audio into a receive signal, the ambient audio potentially including a feedback component; a feedback filter that filters the reproduced signal to obtain an estimated feedback component; a combiner that derives the reproduced signal from the receive signal at least in part by subtracting the estimated feedback component; and a controller that, subject to an adaptation rate, adjusts coefficients of the feedback filter to at least partially cancel the feedback component, the controller varying the adaption rate based at least in part on one or more proximity sensor signals.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.

Abstract: Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.

Abstract: A power semiconductor device includes a substrate having a body region and a drift layer; a trench formed in the substrate; a gate dielectric structure including a first gate insulation layer having a first dielectric constant and a second gate insulation layer having a second dielectric constant different from the first dielectric constant; and a conductive material provided within the trench over the gate dielectric structure.

Abstract: A segmented optoelectronic semiconductor package may help to alleviate stresses resulting from bending that can cause a mechanical defect (e.g., crack) in a detector circuit. The bending can result from thermal growth/shrinkage of parts used in the optical electronic package and may be more pronounced for high aspect ratio detector circuits. The segmentation of the disclosed semiconductor package can create seams that allow the parts to flex without breaking. As a result, the disclosed semiconductor package may facilitate high aspect ratio optical detection over a wide temperature range.

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side. A first side of an optically transmissive lid may be coupled to the second side of the semiconductor die through one or more dams. The packages may also include a light block material around the semiconductor package extending from the first side of the semiconductor die to a second side of the optically transmissive lid. The package may include an opening in the light block material on the second side of the optically transmissive lid that substantially corresponds with an active area of the semiconductor die.

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side. A first side of an optically transmissive lid may be coupled to the second side of the semiconductor die through one or more dams. The packages may also include a light block material around the semiconductor package extending from the first side of the semiconductor die to a second side of the optically transmissive lid. The package may include an opening in the light block material on the second side of the optically transmissive lid that substantially corresponds with an active area of the semiconductor die.

Abstract: Techniques are described for the use of moats for isolating and singulating semiconductor devices formed on a wafer. Described techniques use dielectric films, such as an oxide-nitride film, to coat moat surfaces and provide passivation. The dielectric films may form a junction with a metal contact layer, to reduce electrical overstress that may otherwise occur in the resulting semiconductor devices. To ensure coverage of the moat surfaces, spray coating of a positive photoresist may be used.

Abstract: Implementations of a method of forming a plurality of semiconductor devices on a semiconductor substrate may include: providing a semiconductor substrate having a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface. The method may include processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface. The thickness may be between 100 microns and 575 microns and the size may be 150 mm. The semiconductor substrate may not be coupled with a carrier or support.

Abstract: Implementations of a substrate carrier may include: a top ring configured to enclose an edge of a first side of a substrate; and a bottom support configured to enclose an entire second side and an edge of the second side of the substrate.

Abstract: A method includes forming a plurality of pockets of semiconductor material in a semiconductor substrate. The plurality of pockets are electrically isolated from the semiconductor substrate. The method further involves forming a metal-oxide-semiconductor field-effect transistor (MOSFET) in a pocket of the plurality of pockets, the MOSFET being a vertical trench shielded gate MOSFET. The method further includes forming an electrical connection to a drain region of the MOSFET vertically below a trench and a mesa of the MOSFET.

Abstract: Implementations of a semiconductor package may include a pin coupled to a substrate. The pin may include a titanium sublayer, a nickel sublayer, and one of a silver and tin intermetallic layer or a copper and tin intermetallic layer, the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer having a melting temperature greater than 260 degrees Celsius. The one of the silver and tin intermetallic layer or the copper and tin intermetallic layer may be formed by reflowing a tin layer and one of a silver layer or copper layer with a silver layer of the substrate where the substrate may be directly coupled to the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer. The substrate may include a copper layer that was directly coupled with the silver layer before the reflow.

Abstract: Implementations described herein are related to a semiconductor device package having an improved baseplate. In such an improved baseplate, there is a recess cut out of a region of a surface of the baseplate such that the recess has a first sidewall having a first thickness above a recess base and a second sidewall having a second thickness above the recess base. A substrate, e.g., a direct bonded copper (DBC) substrate, may be attached to the baseplate at a recess base using, e.g., a solder layer between the recess base and a surface of the substrate.

Abstract: Adjusting slope compensation. At least one example embodiment is a method including: operating a switching power converter comprising a charge control switch, the charge control switch configured to control power flow through the switching power converter, and the operating by a circuit controller; measuring, by the circuit controller, an attribute of duty cycle of a first period of the charge control switch; measuring, by the circuit controller, an attribute of duty cycle of a second period of the charge control switch; measuring, by the circuit controller, an attribute of duty cycle of a third period of the charge control switch; determining, by the circuit controller, that the switching power converter is experiencing subharmonic oscillation based on the first, second, and third attributes of duty cycle; and changing, by the circuit controller, an attribute of slope compensation responsive to the determining that the switching power supply is experiencing subharmonic oscillation.