Abstract: A FIR filter (15), comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first transconductance device (30a) configured to generate a first current signal (i1) proportional to the input signal; a first analog switch (41a) commuted in n by a first digital gate signal (?1) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor (45a) when the first digital gate signal has a second value; characterized in that the first digital gate signal (?1) comprises a periodic series of pulses, wherein the pulses have widths proportional to the filter coefficients.

Abstract: A method of characterizing a LoRa modulated signal or any such signals with a plurality of chirps as symbols. It foresees sampling and storing the signal, determining a phase of at least one chirp in the signal, and determining a timing error and/or a frequency error based on the phase, The timing error is extracted by the height of a discontinuous step in the phase at the position of the cyclical shift, while the frequency error is obtained by the slope of the phase. The method can be applied to a dedicated receiver for the characterization of LoRa transmitters.

Abstract: A compound semiconductor integrated circuit is disclosed, which includes biasing circuitry for generating a bias voltage at a bias output node. The biasing circuitry comprises a first circuit branch configured to extend between a defined voltage and a supply voltage. The first circuit branch includes a first transistor configured as a current source to generate a defined current in the first circuit branch and a controllably variable resistance. The bias output node is coupled to the first circuit branch at a first node which is between the controllably variable resistance and the first transistor. The biasing circuitry is operable so that the resistance value of the controllably variable resistance varies with a control voltage so as to vary the value of the bias voltage.

Abstract: A packaged optical receiver, comprising: a photodiode configured to receive an optical signal; a transimpedance amplifier (TIA) coupled to the photodiode; and a signal pin; wherein the optical receiver is configured to receive, via the signal pin, a reset signal; and wherein the optical receiver is configured to output in response to the reset signal, via the signal pin, a received signal strength indication (RSSI) for the received optical signal.

Abstract: After transmitting first electrical signals to a receiver, a transmitter receives a burst absent mode signal from the receiver. While in a ready state, the transmitter receives a signal including a data burst, converts the signal to second electrical signals, including a settled DC offset, and transmits the second electrical signals to the receiver. The receiver transmits the burst absent mode signal to the transmitter after receiving the first electrical signals, detects a presence of the second electrical signals. In response to detecting the presence of the second electrical signals, the receiver removes the DC offset from the second electrical signals to generate output signals, and causes transmitting the output signals to a subsequent device. The receiver removes the DC offset by causing an instruction to discharge AC coupling capacitors. The burst absent mode signal is generated using a host reset instruction or an internally generated instruction.

Abstract: A system may include a recovery circuit that may: receive a first detect signal for a first burst signal and a second detect signal for a second burst signal in a burst mode data path; receive a reference pattern signal from a continuous mode data path; generate a first lock signal locked to the first burst signal or locked to the reference pattern signal, and a second lock signal locked to the second burst signal; and output the reference pattern signal from the recovery circuit during a guard period. The frequency of the recovery circuit may be locked to the frequency of the reference pattern signal during the guard period. The guard period may start based on when the first detect signal de-asserts or when the first lock signal de-asserts. During the guard period, the recovery circuit does not output the first burst signal or the second burst signal.

Abstract: A signal driver may include a plurality of distributed drivers along a differential transmission line. Each of the plurality of the distributed drivers may include: an output tap configured to receive a portion of an incoming signal of the signal driver; and a T-coil connected to an output node of the output tap. The differential transmission line is connected to and intercepted by a first terminal and a second terminal of the T-coil, and a plurality of T-coils of the plurality of the distributed drivers are distributed along and spaced apart on the differential transmission line.

Abstract: Environmental sensor circuit for a portable connected wireless device. The circuit includes a capacitive proximity sensor that determines when a user is close to the portable device. The device also has a magnetic field probe that provides a signal that indicates the position of a permanent magnet. The sensor circuit integrates both a digitizing unit and digital signal processing for the suppression of noise and drive in signals coming from the proximity sensor and from the magnetic field probe.

Abstract: A decision feedback equalizer (DFE) may include a summer configured to receive a signal stream, and a plurality of feedback taps including a first feedback tap connected to the summer. The first feedback tap may include a pre-amplifier, a combined latch and a digital to analog converter (DAC). The pre-amplifier may be configured to be clocked by a first clock signal, wherein the pre-amplifier may be configured to receive an output signal of the summer and to receive a first postcursor generated by the DFE of a previous signal in the signal stream. The combined latch may be configured to be clocked by a first clock signal and a second clock signal. The DAC may be coupled to an output node of the combined latch. The first postcursor may be provided to the pre-amplifier without being provided to the summer.

Abstract: A decision feedback equalizer (DFE) may include a summer configured to receive a signal stream, and a plurality of feedback taps including a first feedback tap connected to the summer. The first feedback tap may include a pre-amplifier, a combined latch and a digital to analog converter (DAC). The pre-amplifier may be configured to be clocked by a first clock signal, wherein the pre-amplifier may be configured to receive an output signal of the summer and to receive a first postcursor generated by the DFE of a previous signal in the signal stream. The combined latch may be configured to be clocked by a first clock signal and a second clock signal. The DAC may be coupled to an output node of the combined latch. The first postcursor may be provided to the pre-amplifier without being provided to the summer.

Abstract: A signal driver may include a variable termination resistor and a signal transmission line. The variable termination resistor may include one or more variable termination resistor units. Each of the one or more variable termination resistor units may include a switch connected to a first end node of the variable termination resistor; a T-coil connected to the switch; a first resistor connected to the first end node of the variable termination resistor and to the T-coil; and a second resistor connected to a second end node of the variable termination resistor and to the T-coil. The signal transmission line may be connected to the second end node of the variable termination resistor.

Abstract: A differential signal driver may include a driver circuit and a feedback loop. The driver circuit may include a first output node coupled to a first termination node for receiving a first termination bias voltage, a second output node coupled to a second termination node for receiving a second termination bias voltage, and a bias network connected to the second output node and to the second termination node. The feedback loop may include a first feedback resistor connected to the first output node at a first end of the first feedback resistor, a second feedback resistor connected to the second output node at a first end of the second feedback resistor, and a feedback amplifier configured to provide a feedback correction current from a common mode voltage to a node within the line from the first output node to the first termination node.

Abstract: The invention relates to a single-inductor multiple-output (SIMO) DC-DC converter (1), comprising: an electrical DC voltage source (Vs) switchable connected to an input node (ni) through an input switch (S1, S2); a plurality of loads (Ro1, Ro2, RoN) each being switchable connected to an output node (no) through one output switch (So1, So2, SoN) of a plurality of output switches (So1, So2, SoN), wherein the electrical DC voltage source (Vs) and the loads (Ro1, Ro2, RoN) are external to the SIMO DC-DC converter (1); an inductor (L) connected to the input node (ni) and the output node (no) and being configured to buffer energy; a control structure arranged to operate in consecutive cycles and being configured to generate control signals for the input switch (S1, S2) and the output switches (So1, So2, SoN), wherein the inductor (L) being energized and de-energized in one cycle of operation (Tcycle) for supplying the plurality of loads (Ro1, Ro2, RoN) with a set of currents (Iact) within the said cycle of opera

Abstract: A variable transimpedance amplifier may include first and second amplifiers. Each of the first and second amplifiers may include a transistor amplifier with a feedback resistor and a capacitor. The output node of the first amplifier may be an output node of the variable transimpedance amplifier. The output node of the second amplifier is not part of the output node of the variable transimpedance amplifier. The open loop gains of the transistor amplifiers may be variable, but the feedback resistor values can be fixed. The transimpedance may be determined by the feedback resistors and a scaling factor proportional to ratio of open loop gains. The transistor amplifiers may share an input transistor. The configuration can provide a high dynamic range of variable transimpedance that is stable over process and operating condition variations, minimize input capacitance loading and noise contribution to small input signals.

Abstract: After transmitting first electrical signals to a receiver, a transmitter receives a burst absent mode signal from the receiver. While in a ready state, the transmitter receives a signal including a data burst, converts the signal to second electrical signals, including a settled DC offset, and transmits the second electrical signals to the receiver. The receiver transmits the burst absent mode signal to the transmitter after receiving the first electrical signals, detects a presence of the second electrical signals. In response to detecting the presence of the second electrical signals, the receiver removes the DC offset from the second electrical signals to generate output signals, and causes transmitting the output signals to a subsequent device. The receiver removes the DC offset by causing an instruction to discharge AC coupling capacitors. The burst absent mode signal is generated using a host reset instruction or an internally generated instruction.

Abstract: A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

Abstract: A radio transmitting device configured to transmit a spread-spectrum radio signal wherein a carrier frequency changes in a predetermined set of radio channels according to a hopping sequence, the radio signal being organized in packets having each a header transmitted at a first channel in the hopping sequence comprising a detection sequence, and payload data encoding a message transmitted at following channels in the hopping sequence.

Abstract: A signal driver may include a variable termination resistor and a signal transmission line. The variable termination resistor may include one or more variable termination resistor units. Each of the one or more variable termination resistor units may include a switch connected to a first end node of the variable termination resistor; a T-coil connected to the switch; a first resistor connected to the first end node of the variable termination resistor and to the T-coil; and a second resistor connected to a second end node of the variable termination resistor and to the T-coil. The signal transmission line may be connected to the second end node of the variable termination resistor.

Abstract: A signal driver may include a plurality of distributed drivers along a differential transmission line. Each of the plurality of the distributed drivers may include: an output tap configured to receive a portion of an incoming signal of the signal driver; and a T-coil connected to an output node of the output tap. The differential transmission line is connected to and intercepted by a first terminal and a second terminal of the T-coil, and a plurality of T-coils of the plurality of the distributed drivers are distributed along and spaced apart on the differential transmission line.

Abstract: A differential signal driver may include a driver circuit and a feedback loop. The driver circuit may include a first output node coupled to a first termination node for receiving a first termination bias voltage, a second output node coupled to a second termination node for receiving a second termination bias voltage, and a bias network connected to the second output node and to the second termination node. The feedback loop may include a first feedback resistor connected to the first output node at a first end of the first feedback resistor, a second feedback resistor connected to the second output node at a first end of the second feedback resistor, and a feedback amplifier configured to provide a feedback correction current from a common mode voltage to a node within the line from the first output node to the first termination node.