Abstract: A system may include a recovery circuit that may: receive a first detect signal for a first burst signal and a second detect signal for a second burst signal in a burst mode data path; receive a reference pattern signal from a continuous mode data path; generate a first lock signal locked to the first burst signal or locked to the reference pattern signal, and a second lock signal locked to the second burst signal; and output the reference pattern signal from the recovery circuit during a guard period. The frequency of the recovery circuit may be locked to the frequency of the reference pattern signal during the guard period. The guard period may start based on when the first detect signal de-asserts or when the first lock signal de-asserts. During the guard period, the recovery circuit does not output the first burst signal or the second burst signal.

Abstract: A signal driver may include a plurality of distributed drivers along a differential transmission line. Each of the plurality of the distributed drivers may include: an output tap configured to receive a portion of an incoming signal of the signal driver; and a T-coil connected to an output node of the output tap. The differential transmission line is connected to and intercepted by a first terminal and a second terminal of the T-coil, and a plurality of T-coils of the plurality of the distributed drivers are distributed along and spaced apart on the differential transmission line.

Abstract: Environmental sensor circuit for a portable connected wireless device. The circuit includes a capacitive proximity sensor that determines when a user is close to the portable device. The device also has a magnetic field probe that provides a signal that indicates the position of a permanent magnet. The sensor circuit integrates both a digitizing unit and digital signal processing for the suppression of noise and drive in signals coming from the proximity sensor and from the magnetic field probe.

Abstract: A decision feedback equalizer (DFE) may include a summer configured to receive a signal stream, and a plurality of feedback taps including a first feedback tap connected to the summer. The first feedback tap may include a pre-amplifier, a combined latch and a digital to analog converter (DAC). The pre-amplifier may be configured to be clocked by a first clock signal, wherein the pre-amplifier may be configured to receive an output signal of the summer and to receive a first postcursor generated by the DFE of a previous signal in the signal stream. The combined latch may be configured to be clocked by a first clock signal and a second clock signal. The DAC may be coupled to an output node of the combined latch. The first postcursor may be provided to the pre-amplifier without being provided to the summer.

Abstract: A decision feedback equalizer (DFE) may include a summer configured to receive a signal stream, and a plurality of feedback taps including a first feedback tap connected to the summer. The first feedback tap may include a pre-amplifier, a combined latch and a digital to analog converter (DAC). The pre-amplifier may be configured to be clocked by a first clock signal, wherein the pre-amplifier may be configured to receive an output signal of the summer and to receive a first postcursor generated by the DFE of a previous signal in the signal stream. The combined latch may be configured to be clocked by a first clock signal and a second clock signal. The DAC may be coupled to an output node of the combined latch. The first postcursor may be provided to the pre-amplifier without being provided to the summer.

Abstract: A signal driver may include a variable termination resistor and a signal transmission line. The variable termination resistor may include one or more variable termination resistor units. Each of the one or more variable termination resistor units may include a switch connected to a first end node of the variable termination resistor; a T-coil connected to the switch; a first resistor connected to the first end node of the variable termination resistor and to the T-coil; and a second resistor connected to a second end node of the variable termination resistor and to the T-coil. The signal transmission line may be connected to the second end node of the variable termination resistor.

Abstract: A differential signal driver may include a driver circuit and a feedback loop. The driver circuit may include a first output node coupled to a first termination node for receiving a first termination bias voltage, a second output node coupled to a second termination node for receiving a second termination bias voltage, and a bias network connected to the second output node and to the second termination node. The feedback loop may include a first feedback resistor connected to the first output node at a first end of the first feedback resistor, a second feedback resistor connected to the second output node at a first end of the second feedback resistor, and a feedback amplifier configured to provide a feedback correction current from a common mode voltage to a node within the line from the first output node to the first termination node.

Abstract: The invention relates to a single-inductor multiple-output (SIMO) DC-DC converter (1), comprising: an electrical DC voltage source (Vs) switchable connected to an input node (ni) through an input switch (S1, S2); a plurality of loads (Ro1, Ro2, RoN) each being switchable connected to an output node (no) through one output switch (So1, So2, SoN) of a plurality of output switches (So1, So2, SoN), wherein the electrical DC voltage source (Vs) and the loads (Ro1, Ro2, RoN) are external to the SIMO DC-DC converter (1); an inductor (L) connected to the input node (ni) and the output node (no) and being configured to buffer energy; a control structure arranged to operate in consecutive cycles and being configured to generate control signals for the input switch (S1, S2) and the output switches (So1, So2, SoN), wherein the inductor (L) being energized and de-energized in one cycle of operation (Tcycle) for supplying the plurality of loads (Ro1, Ro2, RoN) with a set of currents (Iact) within the said cycle of opera

Abstract: A variable transimpedance amplifier may include first and second amplifiers. Each of the first and second amplifiers may include a transistor amplifier with a feedback resistor and a capacitor. The output node of the first amplifier may be an output node of the variable transimpedance amplifier. The output node of the second amplifier is not part of the output node of the variable transimpedance amplifier. The open loop gains of the transistor amplifiers may be variable, but the feedback resistor values can be fixed. The transimpedance may be determined by the feedback resistors and a scaling factor proportional to ratio of open loop gains. The transistor amplifiers may share an input transistor. The configuration can provide a high dynamic range of variable transimpedance that is stable over process and operating condition variations, minimize input capacitance loading and noise contribution to small input signals.

Abstract: After transmitting first electrical signals to a receiver, a transmitter receives a burst absent mode signal from the receiver. While in a ready state, the transmitter receives a signal including a data burst, converts the signal to second electrical signals, including a settled DC offset, and transmits the second electrical signals to the receiver. The receiver transmits the burst absent mode signal to the transmitter after receiving the first electrical signals, detects a presence of the second electrical signals. In response to detecting the presence of the second electrical signals, the receiver removes the DC offset from the second electrical signals to generate output signals, and causes transmitting the output signals to a subsequent device. The receiver removes the DC offset by causing an instruction to discharge AC coupling capacitors. The burst absent mode signal is generated using a host reset instruction or an internally generated instruction.

Abstract: A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

Abstract: A radio transmitting device configured to transmit a spread-spectrum radio signal wherein a carrier frequency changes in a predetermined set of radio channels according to a hopping sequence, the radio signal being organized in packets having each a header transmitted at a first channel in the hopping sequence comprising a detection sequence, and payload data encoding a message transmitted at following channels in the hopping sequence.

Abstract: A signal driver may include a variable termination resistor and a signal transmission line. The variable termination resistor may include one or more variable termination resistor units. Each of the one or more variable termination resistor units may include a switch connected to a first end node of the variable termination resistor; a T-coil connected to the switch; a first resistor connected to the first end node of the variable termination resistor and to the T-coil; and a second resistor connected to a second end node of the variable termination resistor and to the T-coil. The signal transmission line may be connected to the second end node of the variable termination resistor.

Abstract: A signal driver may include a plurality of distributed drivers along a differential transmission line. Each of the plurality of the distributed drivers may include: an output tap configured to receive a portion of an incoming signal of the signal driver; and a T-coil connected to an output node of the output tap. The differential transmission line is connected to and intercepted by a first terminal and a second terminal of the T-coil, and a plurality of T-coils of the plurality of the distributed drivers are distributed along and spaced apart on the differential transmission line.

Abstract: A differential signal driver may include a driver circuit and a feedback loop. The driver circuit may include a first output node coupled to a first termination node for receiving a first termination bias voltage, a second output node coupled to a second termination node for receiving a second termination bias voltage, and a bias network connected to the second output node and to the second termination node. The feedback loop may include a first feedback resistor connected to the first output node at a first end of the first feedback resistor, a second feedback resistor connected to the second output node at a first end of the second feedback resistor, and a feedback amplifier configured to provide a feedback correction current from a common mode voltage to a node within the line from the first output node to the first termination node.

Abstract: A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

Abstract: A leadframe is formed by chemically half-etching a sheet of conductive material. The half-etching exposes a first side surface of a first contact of the leadframe. A solder wettable layer is plated over the first side surface of the first contact. An encapsulant is deposited over the leadframe after plating the solder wettable layer.

Abstract: A methods and apparatuses for supporting device-to-device (D2D) communication in a wireless network is provided. According to embodiments, during a period where a D2D device 1 (D1) and a D2D device 2 (D2) are available for active D2D communications therebetween and when D2 identifies a need for a second communication with at least one of a base station or a different D2D device, the method includes transmitting, by D2, a D2D communication not available message (DNAM) to D1. The DNAM indicates that one or both of D1 and D2 are unavailable for active D2D communications therebetween. Upon receipt of the DNAM by D1, the method further includes transitioning, by D1, to a listening mode for receiving at least a D2D communication available message (DAM) from D2. The DAM indicates that D1 and D2 are available for active D2D communications therebetween.

Abstract: A leadframe is formed by chemically half-etching a sheet of conductive material. The half-etching exposes a first side surface of a first contact of the leadframe. A solder wettable layer is plated over the first side surface of the first contact. An encapsulant is deposited over the leadframe after plating the solder wettable layer.

Abstract: A TVS circuit having a first diode with a cathode coupled to a first terminal and an anode coupled to a first node. A second diode has an anode coupled to a second node and a cathode coupled to a third node. A third diode is coupled between the first node and second node. A fourth diode is coupled between the first node and third node. A fifth diode is coupled between the second node and a second terminal. A sixth diode is coupled between the second terminal and the third node. A seventh diode can be coupled between the second terminal and an intermediate node between the fifth diode and sixth diode. The first diode is disposed on a first semiconductor die, while the second diode is disposed on a second semiconductor die. Alternatively, the first diode and second diode are disposed on a single semiconductor die.