Abstract: The present invention proposed a weighted Centroid Localisation (WCL) algorithm, which does the location estimation based on the known positions of the gateways and the measurements times of arrival (TOA) at the gateways. The algorithm computes the weight of the gateway based on their rank when the gateways are sorted by their TOA. Simulations have demonstrated the algorithm's robustness under different multipath/fading channel conditions and its good location performance.

Abstract: A circuit controls a dynamic time constant to remove DC offset from a received optical data signal. The circuit has a first capacitor coupled between a first terminal and a second terminal. A first resistance network is coupled between the second terminal and a reference voltage. A control circuit has a first output coupled to a control input of the first resistance network. The control circuit monotonically increases an effective resistance of the first resistance network to increase the dynamic time constant. The first resistance network has a resistor coupled to the second terminal, and a transistor with a first conduction terminal coupled to the resistor, a second conduction terminal coupled to the reference voltage, and a control terminal coupled to the first output of the control circuit. The first capacitor has a variable capacitance. The monotonic increase in the dynamic time constant can be linear or non-linear.

Abstract: A hopping spread-spectrum wireless network for IoT applications with mobile device that have unsynchronized local frequency references. The transmitters use hopping sequences defined in term of the relative differences of frequencies, in such a manner that a receiver can determine the hopping sequence of a transmission despite the presence of a large frequency error.

Abstract: A signal detection circuit has a first differential amplifier including a first input coupled for receiving a data signal, and a second input coupled for receiving a threshold signal. A current steering circuit is coupled to an output of the first differential amplifier to establish a threshold for the first differential amplifier. A latch has an input coupled to the output of the first differential amplifier for latching a signal detect. A second amplifier has an input coupled to the output of the first differential amplifier and an output coupled to the input of the latch. A third amplifier has an input coupled to the output of the first differential amplifier and an output providing the data signal. The current steering circuit can be disabled which removes the need for the third amplifier as the data signal path is through second amplifier.

Abstract: A ranging and positioning system comprising transmitters and receiver nodes communicating together by chirp-modulated radio signals, that have a ranging mode in which ranging exchange of signals takes place between a master device and a slave device that leads to the evaluation of the range between them. The slave is arranged for recognizing a ranging request and transmit back a ranging response containing chirps that precisely aligned in time and frequency with the chirps in the ranging requests, whereupon the master can receive the ranging response, analyze the time and frequency the chirps contained therein with respect to his own time reference, and estimate a range to the slave.

Abstract: A circuit detects a digital pattern with a first counter having an input receiving a digital pattern, and an output providing an output signal after detecting a first number of pulses during a first time period. A latch has an input coupled to the output of the first counter for latching the output signal of the first counter. A second counter has an input receiving the digital pattern, and an output providing an output signal after detecting a second number of pulses during a second time period. A logic gate has a first input coupled the output of the first counter, and a second input coupled to the output of the second counter, and an output coupled to the input of the latch. An amplitude detection circuit has an input coupled for receiving the digital pattern and an output coupled to the input of the first counter.

Abstract: An integrated circuit has a CMOS signal path coupled for receiving a data signal. A compensation circuit is coupled to a power supply rail of the CMOS signal path for injecting a compensation current into the power supply rail. The compensation circuit can be a charge pump operating in response to the data signal to inject the compensation current into the power supply rail each transition of the data signal. The compensation circuit can be a replica CMOS signal path to inject the compensation current into the power supply rail each transition of the data signal. The compensation circuit can be a voltage regulator and current mirror including an input coupled to the voltage regulator. The replica CMOS signal path receives an operating potential from the voltage regulator. An output of the current mirror injects the compensation current into the power supply rail each transition of the data signal.

Abstract: A tag is provided that includes a battery having a printed anode and cathode. A printed circuit connection layer is formed in one of the anode or the cathode. A printed antenna is formed in one of the anode or the cathode. A low-power transmitter coupled to the circuit connection layer.

Abstract: A driver circuit has a plurality of transistors in a cascode arrangement. A passive biasing circuit is coupled to a gate terminal of a first transistor of the plurality of transistors. The passive biasing circuit has a first resistor coupled to a circuit node to provide a first biasing signal, a first capacitor coupled between the circuit node and a power supply conductor, a second resistor coupled between the circuit node and a drain terminal of the first transistor, and a third resistor coupled between the circuit node and a source terminal of the first transistor. A second transistor has a gate terminal coupled for receiving a data signal which controls an optical device.

Abstract: An automatic gain control circuit controls a gain of a burst mode amplifier. A peak detector includes an input coupled to an output of the amplifier. A plurality of resistors is coupled in series between an input of the first amplifier and the output of the first amplifier for setting the gain of the amplifier. A first gain stage is responsive to an output signal of the peak detector for disabling a first resistor of the plurality of resistors to alter the gain of the first amplifier. A second gain stage is responsive to the output signal of the peak detector for disabling a second resistor of the plurality of resistors to alter the gain of the first amplifier. A comparator responsive to the output signal of the peak detector causes a pulse generator to enable the first gain stage and second gain stage each burst mode.

Abstract: A wireless charging receiver that provides power delivered from a transmitter over a wireless path. The receiver includes a rectifier circuit, an LC circuit coupled to the rectifier circuit and the transmitter, a single switch modulation circuit coupled to the rectifier circuit and the LC circuit, an output circuit coupled to the rectifier circuit. The receiver further comprises an in-band controller coupled to the LC circuit and the single switch modulation circuit operational to detect a reflected parameter from incident RF power. A resistance value of the single switch modulation circuit can be set in response to a detected parametric value of the LC circuit. The resistance value can be set to cause the rectifier circuit to generate one of a stable RDCV value, an increased RDCV value, and a decreased RDCV value with respect to a normal PDC value in response to the received RF power.

Abstract: A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load. A parallel protection circuit is electrically coupled between the transmission line and a ground node. The parallel protection circuit can include a transient-voltage-suppression (TVS) diode.

Abstract: Method of timing, in a receiver, a radio signal generated in and transmitted from a transmitter, the radio signal comprising a series of frequency chirps, the system including: receiving the radio signal from the transmitter; synthesizing projection vectors comprising a series of frequency chirps that are a complex-conjugate image of those comprised in the radio signal the projection vectors being time-shifted relative to one another by determined shift intervals of time; multiplying the received radio signal by the projection vectors and accumulating the results; interpolating the accumulating results to determine a peak time shift.

Abstract: A photodiode current comparison circuit has a first current source coupled to a circuit node configurable to operate in a first mode, a second current source coupled to the circuit node configurable to operate in a second mode opposite the first mode, and a third current source switchable to route a current to the circuit node in response to a data signal using a transistor coupled between the circuit node and the third current source. A photodiode is coupled to the circuit node. In a first configuration, an anode of the photodiode is coupled to the circuit node and a cathode of the photodiode is coupled to a power supply terminal. In a second configuration, a cathode of the photodiode is coupled to the circuit node and an anode of the photodiode is coupled to a power supply terminal. An amplifier provides an error signal of the photodiode.

Abstract: A circuit controls a dynamic time constant to remove DC offset from a received optical data signal. The circuit has a first capacitor coupled between a first terminal and a second terminal. A first resistance network is coupled between the second terminal and a reference voltage. A control circuit has a first output coupled to a control input of the first resistance network. The control circuit monotonically increases an effective resistance of the first resistance network to increase the dynamic time constant. The first resistance network has a resistor coupled to the second terminal, and a transistor with a first conduction terminal coupled to the resistor, a second conduction terminal coupled to the reference voltage, and a control terminal coupled to the first output of the control circuit. The first capacitor has a variable capacitance. The monotonic increase in the dynamic time constant can be linear or non-linear.

Abstract: A mobile device has a proximity sensor. A compensation value of the proximity sensor is determined. The compensation value is compared to a reference compensation value to determine validity of the compensation value. A capacitance of the proximity sensor is measured. A value of the capacitance of the proximity sensor is adjusted based on the compensation value. A coefficient defining a relationship between a capacitance of the proximity sensor and a temperature of the mobile device is calculated. A temperature sensor is coupled to the proximity sensor. The temperature of the mobile device is measured. A value of the capacitance of the proximity sensor is adjusted based on the coefficient and the temperature of the mobile device. The adjusted capacitance value is compared to a threshold capacitance value to determine proximity of an object to the mobile device. A radio frequency signal is adjusted by detecting proximity.

Abstract: A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load. A parallel protection circuit is electrically coupled between the transmission line and a ground node. The parallel protection circuit can include a transient-voltage-suppression (TVS) diode.

Abstract: A method for controlling power delivery from a transmitter to a receiver, comprising generating a control at a processor to actuate a distance measurement device. Transmitting the control to the distance measurement device. Activating the distance measurement device to measure a distance between a transmitter and a receiver. Transmitting a data packet from the distance measurement device to the processor that contains a plurality of data fields that have a value that represents the distance. Determining whether the distance is less than a predetermined threshold using the processor. Generating an error signal if the distance is less than the predetermined threshold to prevent the transmitter from generating an electromagnetic field that would cause damage to the receiver. Setting a ping signal strength as a function of the distance. Generating an electromagnetic field as a function of the ping signal strength.

Abstract: An OMA controller circuit utilizes a first ADC with an input coupled for receiving a residual error signal indicating a difference between a monitoring signal and a target data signal. A second ADC has an input coupled for receiving the target data signal. A first digital filter has an input coupled to an output of the first ADC, and a second digital filter has an input coupled to an output of the second ADC. A digital multiplier has a first input coupled to an output of the first digital filter and a second input coupled to an output of the second digital filter. An integrator has an input coupled to an output of the digital multiplier and an output providing an average error signal with sign and magnitude. The digital multiplier uses a four quadrant multiplier to perform a cross-correlation on the residual error and the target data signal.

Abstract: An automatic gain control circuit controls a gain of a burst mode amplifier. A peak detector includes an input coupled to an output of the amplifier. A plurality of resistors is coupled in series between an input of the first amplifier and the output of the first amplifier for setting the gain of the amplifier. A first gain stage is responsive to an output signal of the peak detector for disabling a first resistor of the plurality of resistors to alter the gain of the first amplifier. A second gain stage is responsive to the output signal of the peak detector for disabling a second resistor of the plurality of resistors to alter the gain of the first amplifier. A comparator responsive to the output signal of the peak detector causes a pulse generator to enable the first gain stage and second gain stage each burst mode.