Patents Assigned to Sensor Electronics Technology, Inc.
  • Patent number: 10245338
    Abstract: A solution for generating ultraviolet diffusive radiation is provided. A diffusive ultraviolet radiation illuminator includes at least one ultraviolet radiation source located within a reflective cavity that includes a plurality of surfaces. At least one of the plurality of surfaces can be configured to diffusively reflect at least 70% of the ultraviolet radiation and at least one of the plurality of surfaces can be configured to transmit at least 30% of the ultraviolet radiation and reflect at least 10% of the ultraviolet radiation.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: April 2, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Saulius Smetona, Alexander Dobrinsky, Yuri Bilenko, Michael Shur
  • Patent number: 10243100
    Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: March 26, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Jinwei Yang, Remigijus Gaska, Mikhail Gaevski
  • Patent number: 10236415
    Abstract: A contact to a semiconductor heterostructure is described. In one embodiment, there is an n-type semiconductor contact layer. A light generating structure formed over the n-type semiconductor contact layer has a set of quantum wells and barriers configured to emit or absorb target radiation. An ultraviolet transparent semiconductor layer having a non-uniform thickness is formed over the light generating structure. A p-type contact semiconductor layer having a non-uniform thickness is formed over the ultraviolet transparent semiconductor layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: March 19, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Alexander Dobrinsky
  • Patent number: 10237929
    Abstract: A solid-state light source (SSLS) with an integrated electronic modulator is described. A device can include a SSLS having an active p-n junction region is formed within the SSLS for electron-hole pair recombination and light emission. the active p-n junction region can include a n-type semiconductor layer, a p-type semiconductor layer and a light generating structure formed there between. A pair of current supply electrodes can be formed to receive a drive current from a current supply source that drives the SSLS. A field-effect transistor (FET) modulator can be monolithically integrated with the SSLS for modulation thereof. The FET modulator can receive a modulation voltage from a modulation voltage source. The modulation voltage includes voltage pulses having a pulse amplitude and polarity to turn on and off current flowing through the FET modulator. These voltage pulses enable the FET modulator to control the drive current supplied to the SSLS.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 19, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Alexander Dobrinsky
  • Patent number: 10224456
    Abstract: A method of fabricating a light emitting diode, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer, is provided. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Maxim S. Shatalov, Michael Shur, Alexander Dobrinsky
  • Patent number: 10224408
    Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Mikhail Gaevski, Grigory Simin, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20190056538
    Abstract: A diffusive layer including a laminate of a plurality of transparent films is provided. At least one of the plurality of transparent films includes a plurality of diffusive elements with a concentration that is less than a percolation threshold. The plurality of diffusive elements are optical elements that diffuse light that is impinging on such element. The plurality of diffusive elements can be diffusively reflective, diffusively transmitting or combination of both. The plurality of diffusive elements can include fibers, grains, domains, and/or the like. The at least one film can also include a powder material for improving the diffusive emission of radiation and a plurality of particles that are fluorescent when exposed to radiation.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Michael Shur
  • Patent number: 10211048
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: February 19, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Wenhong Sun, Rakesh Jain, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
  • Publication number: 20190039920
    Abstract: A solution for disinfecting a fluid, colloid, mixture, and/or the like using ultraviolet radiation is provided. An ultraviolet transparent enclosure can include an inlet and an outlet for a flow of media to be disinfected. The ultraviolet transparent enclosure can include a material that is configured to prevent biofouling within the ultraviolet transparent enclosure. A set of ultraviolet radiation sources are located adjacent to the ultraviolet transparent enclosure and are configured to generate ultraviolet radiation towards the ultraviolet transparent enclosure.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 7, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Saulius Smetona, Timothy James Bettles, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10197750
    Abstract: A light guiding structure is provided. The structure includes an anodized aluminum oxide (AAO) layer and a fluoropolymer layer located immediately adjacent to a surface of the AAO layer. Light propagates through the AAO layer in a direction substantially parallel to the fluoropolymer layer. An optoelectronic device can be coupled to a surface of the AAO layer, and emit/sense light propagating through the AAO layer. Solutions for fabricating the light guiding structure are also described.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10199531
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10199537
    Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10199536
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10199535
    Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20190030196
    Abstract: A solution for disinfecting an ultraviolet transparent structure and/or an item placed on or near the structure is provided. The solution can utilize a set of ultraviolet radiation sources configured to generate ultraviolet radiation through the internal surface of the ultraviolet transparent structure towards the external surface and out to an ambient environment for disinfection of the external surface and/or a targeted item. A first set of sources can generate a scattered type of radiation that uniformly disinfects the external surface of the ultraviolet transparent structure and a second set of sources can generate a focused type of radiation that disinfects at least one portion of the targeted item. A control system can direct the first set of sources to generate the scattered radiation towards the external surface of the ultraviolet transparent structure and direct the second set of sources to generate the focused radiation at the targeted item.
    Type: Application
    Filed: September 26, 2018
    Publication date: January 31, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Yuri Bilenko, Alexander Dobrinsky, Michael Shur
  • Publication number: 20190030477
    Abstract: A system for providing ultraviolet treatment of volatile organic compounds (VOCs) is disclosed. The system can include a first gas conduit to carry a stream of gas having VOCs and a second gas conduit to carry a second stream of gas containing a partial pressure of water vapor. A gas treatment unit can be coupled to the first gas conduit and the second gas conduit. The gas treatment unit can form hydroxyl radicals from the water vapor in the stream of gas carried by the second gas conduit and inject the radicals in the first gas conduit to decrease the presence of the VOCs. The gas treatment unit can include a photocatalyst component and at least one ultraviolet radiation source to irradiate the photocatalyst component with ultraviolet radiation. To this extent, the irradiated photocatalyst component disassociates the gas containing the water vapor to form the hydroxyl radicals.
    Type: Application
    Filed: June 5, 2018
    Publication date: January 31, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventor: Maxim S. Shatalov
  • Publication number: 20190035968
    Abstract: A semiconductor heterostructure including a polarization doped region is described. The region can correspond to an active region of a device, such as an optoelectronic device. The region includes an n-type semiconductor side and a p-type semiconductor side and can include one or more quantum wells located there between. The n-type and/or p-type semiconductor side can be formed of a group III nitride including aluminum and indium, where a first molar fraction of aluminum nitride and a first molar fraction of indium nitride increase (for the n-type side) or decrease (for the p-type side) along a growth direction to create the n- and/or p-polarizations.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Michael Shur
  • Patent number: 10190973
    Abstract: An integrated ultraviolet analyzer is described. The integrated ultraviolet analyzer can include one or more ultraviolet analyzer cells, each of which includes one or more ultraviolet photodetectors and one or more solid state light sources, which are monolithically integrated. The solid state light source can be operated to emit ultraviolet light, at least some of which passes through an analyzer active gap and irradiates a light sensing surface of the ultraviolet photodetector. A medium to be evaluated can be present in the analyzer active gap and affect the ultraviolet light as it passes there through, thereby altering an effect of the ultraviolet light on a ultraviolet photodetector.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 29, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Alexander Dobrinsky
  • Publication number: 20190027651
    Abstract: A contact for solid state light sources is described. The solid state light source can include an active region, such as a light emitting multiple quantum well, and a semiconductor layer, such as a p-type layer, from which carriers (e.g., holes) enter the active region. A contact can be located adjacent to the semiconductor layer and include a plurality of small area contacts extending only partially through the semiconductor layer. The plurality of small area contacts can have a characteristic lateral size at an interface between the small area contact and the semiconductor layer equal to or smaller than a characteristic depletion region width for the plurality of small area contacts.
    Type: Application
    Filed: October 31, 2017
    Publication date: January 24, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Alexander Dobrinsky
  • Publication number: 20190027650
    Abstract: An opto-electronic device with two-dimensional injection layers is described. The device can include a semiconductor structure with a semiconductor layer having one of an n-type semiconductor layer or a p-type semiconductor layer, and a light generating structure formed on the semiconductor layer. A set of tilted semiconductor heterostructures is formed over the semiconductor structure. Each tilted semiconductor heterostructure includes a core region, a set of shell regions adjoining a sidewall of the core region, and a pair of two-dimensional carrier accumulation (2DCA) layers. Each 2DCA layer is formed at a heterointerface between one of the sidewalls of the core region and one of the shell regions. The sidewalls of the core region, the shell regions, and the 2DCA layers each having a sloping surface, wherein each 2DCA layer forms an angle with a surface of the semiconductor structure.
    Type: Application
    Filed: September 26, 2018
    Publication date: January 24, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Alexander Dobrinsky