Abstract: Disclosed are an n-type semiconductor including compound represented by Chemical Formula 1 or Chemical Formula 2, an image sensor, and an electronic device. In Chemical Formula 1 and Chemical Formula 2, each substituent is as defined in the detailed description.

Abstract: A method and apparatus with pruning are disclosed. A method is performed by an apparatus including a processor, the method includes determining weight importance of a trained neural network, receiving a constraint condition related to an operation resource, and determining, in accordance with the constraint condition, a pruning mask for maximizing the weight importance of the trained neural network.

Abstract: In a method of coating a photoresist, the photoresist may be provided to an upper surface of a rotating wafer. A hovering solution may be injected to an edge portion of the photoresist under a condition that the hovering solution may be hovered with respect to the edge portion of the photoresist with an air layer being interposed between the hovering solution and the edge portion of the photoresist to limit and/or prevent a bead of the photoresist from being formed on an edge portion of the upper surface of the wafer. Thus, the photoresist having a uniform thickness may be coated on the upper surface of the wafer to improve a yield of a semiconductor device by increasing an effective area of the edge portion of the wafer.

Abstract: A processor-implemented accelerator method includes: reading, from a memory, an instruction to be executed in an accelerator; reading, from the memory, input data based on the instruction; and performing, on the input data and a parameter value included in the instruction, an inference task corresponding to the instruction.

Abstract: A method and apparatus with neural network control are provided. In one general aspect, a method is performed by at least one processor of an apparatus, the method includes selecting neural networks from among available neural networks with respective input image resolutions, including plural resolutions, wherein the selected neural networks are selected based on a sum of amounts of mutual information between the selected neural networks being minimal and based on a limiting condition of a use of the available neural networks, and configuring the available neural networks to perform an inference on input data, wherein the configuring is based on the combination of the selected neural networks.

Abstract: A processor-implemented method of a neural network includes obtaining intermediate pooling results, respectively corresponding to sub-pooling kernels obtained by decomposing an original pooling kernel, by performing a pooling operation on input pixels included in a current window in an input feature map with the sub-pooling kernels, obtaining a final pooling result corresponding to the current window by post-processing the intermediate pooling results, and determining an output pixel value of an output feature map, based on the final pooling result, wherein the current window is determined according to the original pooling kernel having been slid, according to a raster scan order, in the input feature map.

Abstract: A spiking neural network device comprises at least one NAND cell string including a first NAND cell string that includes a string select transistor and a plurality of nonvolatile memory cells between a bit line and a ground select line, a string control circuit configured to generate a string selection signal to turn on the string select transistor in response to an input spike, a word line decoder configured to generate a word line selection signal for selecting a word line of a plurality of word lines for each of the plurality of nonvolatile memory cells in response to the input spike, a plurality of sensing circuits connected to the bit line, respectively corresponding to the plurality of word lines, each sensing circuit configured to generate an output spike according to a current transmitted through the bit line when a corresponding word line is selected, a plurality of switch transistors, each configured to connect one of the plurality of sensing circuits to the bit line according to a switch selection

Abstract: A pressure sensor includes: a first substrate; a second substrate having an inner surface and a touch surface that is opposite to the inner surface, wherein the inner surface faces the first substrate with a resistance sensing space therebetween; a first electrode and a second electrode, which are arranged spaced apart from each other in the resistance sensing space; and a piezoresistive pattern arranged between the first electrode and the second electrode and disposed in the resistance sensing space, wherein the piezoresistive pattern includes a porous elastic support and a plurality of conductive carbon structures dispersed in the porous elastic support.

Abstract: A processor-implemented data processing method includes encoding a plurality of weights of a filter of a neural network using an inverted two's complement fixed-point format; generating weight data based on values of the encoded weights corresponding to same filter positions of a plurality of filters; and performing an operation on the weight data and input activation data using a bit-serial scheme to control when to perform an activation function with respect to the weight data and input activation data.

Abstract: An apparatus includes a processor configured to generate each of intermediate representation codes corresponding to each of a plurality of loop structures obtained that corresponds to a neural network computation based on an input specification file of hardware; schedule instructions included in each of the intermediate representation codes corresponding to the plurality of loop structures; select, based on latency values predicted according to scheduling results of the intermediate representation codes, any one code among the intermediate representation codes; and allocate, based on a scheduling result of the selected intermediate representation code, instructions included in the selected intermediate representation code to resources of the hardware included in the apparatus.

Abstract: An apparatus includes: one or more processors configured to: generate packed data by performing data packing on an encrypted image; and perform a homomorphic encryption operation based on the packed data and a weight.

Abstract: The present disclosure relates to a binder for a solid-state battery and a manufacturing method thereof. The binder may include a polymer comprising a carbonyl group and a linker comprising amino groups at both ends.

Abstract: An electronic device includes: a state observer configured to observe a state of the electronic device according to an environment interactable with the electronic device; one or more processors configured to: determine a skill based on the observed state; determine a goal based on the determined skill and the observed state; and determine, based on the state and the determined goal, an action causing a linear state transition of the electronic device in a direction toward the determined goal in a state space; and a controller configured to control an operation of the electronic device based on the determined action.

Abstract: A lithography method using a multiscale simulation includes estimating a shape of a virtual resist pattern for a selected resist based on a multiscale simulation; forming a test resist pattern by performing an exposure process on a layer formed of the selected resist; determining whether an error range between the test resist pattern and the virtual resist pattern is in an allowable range; and forming a resist pattern on a patterning object using the selected resist when the error range is in the allowable range. The multiscale simulation may use molecular scale simulation, quantum scale simulation, and a continuum scale simulation, and may model a unit lattice cell of the resist by mixing polymer chains, a photo-acid generator (PAG), and a quencher.

Abstract: An electronic device is provided. The electronic device includes a communication circuit and a processor. The processor may be configured to obtain information on the number of predicted abnormal terminals, allocate different resources respectively to a plurality of terminal groups, wherein the number of the plurality of terminal groups is greater than the number of predicted abnormal terminals, obtain learning data of each of the plurality of terminal groups, and identify a final terminal group among the plurality of terminal groups, based on the learning data.

Abstract: An object tracking learning system includes a first neural network module that expresses and learns a first parameter for an input image from a first type to a second type and outputs the learned result as a first learning result, a second neural network module that removes and learns a connection of a part of a second parameter for the input image and outputs the learned result as a second learning result, a prediction module that generates a prediction value for an object of the input image from a summation result obtained by summing the first learning result and the second learning result, and an optimization module that updates the first parameter and the second parameter based on the prediction value.

Abstract: An image deblurring method and apparatus are provided. The image deblurring method includes generating a primary feature representation on a first blur point in an input image and offset information on similar points of the first blur point by encoding the input image by implementing an encoding model, generating secondary feature representations on the similar points by applying the offset information to the primary feature representation, and generating an output image, based on the secondary feature representations and the offset information, by implementing an implicit function model.

Abstract: A processor-implemented method with image processing includes: providing retouch result candidates of an input image to a user in response to applying vector value candidates to a style vector; determining a vector value of the style vector based on a selection of the user for the retouch result candidates; determining an adjustment parameter set corresponding to the determined vector value of the style vector; and generating a retouch result by adjusting the input image based on the adjustment parameter set.

Abstract: A semiconductor device includes a delay compensation circuit and a bias control circuit. The delay compensation circuit includes a variable delay circuit configured to generate an output signal by delaying an input signal and configured to compensate, according to a first bias control signal, for delay fluctuation caused by fluctuation of a power supply voltage between a first power source and a second power source. The bias control circuit is configured to generate the first bias control signal to compensate for the delay fluctuation.

Abstract: A device includes: a comparator; an exclusive-NOR (XNOR) gate; an accumulator; and a multiplication and accumulation (MAC) operator, wherein a basic block of a neural network comprises a first batch normalization layer, a quantization layer, a convolution layer, an active layer, and a second batch normalization layer, and wherein the basic block is driven by the device by a combination of a first batch normalization operation, a sign function operation, a bitwise convolution operation, an activation function operation, a second batch normalization operation, and a residual connection operation.