Abstract: A heat sink and method for heat sinking a package containing electronic components is described. The heat sinking is accomplished by use of a cooling plate located beneath a circuit board. The package having leads extending from more than one side of the package is positioned on the cooling plate so that the leads from the sides of the package can be electrically coupled to conductors on the circuit board wherein the circuit board is disposed about at least two and preferably three sides of the package. The package is secured to the cooling plate by a spring clip. The spring clip permits flexible positioning of the package relative to the cooling plate including positioning the package in close proximity of the edge of the cooling plate. Thermal conduction between the package and the cooling plate can be enhanced by the presence of a compressible thermally-conducting material.

Abstract: A semiconductor component package comprises a metal plate and a synthetic resin housing or body. The plate is formed with an aperture by which it can be secured to a heat sink, generally a metal plate. Around the aperture is a weakened annular portion produced by shearing. When the package housing is secured to a surface which is not completely flat, mechanical stressing due to the tightening of the screw coupling is limited to the weakened annular portion and is not transmitted to the resin housing and to the elements therein.

Abstract: The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n.sup.+ diffusion which is closed and isolated from those of the other cells of the same memory.

Abstract: The microcomputer is assembled by association of a variable plurality of rectangular functional modules having a fixed first dimension and a variable second dimension. Common busses electrically connect the various modules automatically.

Abstract: A MOS power structure made up of at least one MOS cell with gate electrode, drain electrode, source electrode, well-region and of a bi-polar parasitic transistor provided with a protective device for the gate and drain against overvoltages. The protective device consists of a further bi-polar transistor with optional addition of a zener diode.

Abstract: This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

Abstract: A decontamination system for processes for deposition, etching and/or growth of high purity films, particularly applicable to semiconductor technology.After introducing the products concerned with a process into a chamber and after creating a vacuum in the chamber, the chamber is decontaminated by a series of intermittent inflows of non-contaminating gas and subsequent pressure varying operations.

Abstract: A method for correctly positioning a metallic plate supporting a semiconductor chip in a mold used for encapsulation, wherein according to a first solution, at least a pair of retractable locating pins are utilized together with a lead connected to the supporting plate. The ends of the locating pins are retracted in the final phase of encapsulation, from the surfaces of the plate, whereas in the initial phase they are in direct contact with the surfaces. According to a second solution, a pair of clamping pins are indirectly connected to the plate through the interposition of insulating thicknessings.

Abstract: This power transistor comprises a plurality of elementary transistors, also indicated as "fingers", having their emitter terminals mutually connected and forming a common emitter terminal, collector terminals also mutually connected and forming a common collector terminal, and base terminals connected to at least one current source. Each elementary transistor is part of a circuit comprising a diode forming, together with the elementary transistor, a current mirror, so that the collector current passing through the elementary transistor is far less sensitive to the temperature gradients which originate inside the power transistor.

Abstract: Disclosed is a monolithic integrated semiconductor device which may contain specimens of seven different circuit components; namely: lateral N-MOS and lateral P-MOS transistors (CMOS), vertical N-DMOS and vertical P-DMOS transistors, vertical NPN bipolar transistors, vertical PNP bipolar transistors with isolated collector and low leakage junction diodes as well as a process for fabricating such a device.

Abstract: A power-on reset circuit for supplying a reset pulse when a supply voltage rises above a preset threshold includes a reference voltage generator connected between the supply voltage and ground for supplying a reference signal having a constant preset value when the supply voltage is greater than the preset threshold. A supply follower provides an input signal which follows the supply voltage with a preset reduction factor. A bistable comparator having a first input driven by the reference signal and a second input driven by the input signal switches from a first state to a second state when the input signal exceeds the reference signal.

Abstract: An apparatus and a relative method which permit carrying out a complete cycle of functional tests and parametric measurements on EPROM type semiconductor devices during their permanence inside a burn-in chamber, thus greatly reducing the time necessary for testing and classifying the devices, besides ensuring a higher reliability. The system utilizes special "intelligent" cards, i.e., provided with a card microprocessor which may be connected to a supervisory system's CPU directing the test and classification process of the devices.

Abstract: CMOS logic circuit with one or more inputs has at least a complementary pair of transistors, the N-channel driver transistor having a gate directly connected to an input while the P-channel load transistor having a gate connected to the output of the second one of two inverters connected in cascade, the input of the first inverter being connected to the input of the circuit. Using two signal inverting stages or inverters for mirroring the input signal on the gate of the load P-channel transistor of the circuit pair permits the defining of the triggering threshold of the circuit with great freedom, the obtaining of a greater switching speed and the reduction of power dissipation under stand-by conditions. The invention is particularly suited for HCT circuits.

Abstract: A telephone circuit, which may be monolithically integrated, for supplying ringing signals to a subscriber's telephone line and for detecting an off the hook condition during ringing, including a logic control circuit connected to exchange components which control the supply of the ringing signals and determine their rhythm. The logic control circuit is connected to a circuit for detecting direct current on the line and a current comparator for generating a signal when the value of the line current exceeds a predetermined current value. This signal is also supplied to the exchange components via a transfer circuit to inform them that an off the hook condition has taken place. The logic control circuit is connected to a timing signal generator which synchronizes its functions with times in which the ringing signal has a zero amplitude, and is connected to a signal amplifier circuit which supplies the ringing signals to the line and to the transfer circuit.

Abstract: A voltage divider is placed between a supply terminal and ground and an intermediate node is connected to the word line to ensure a precharging voltage to the word line which is lower than the supply voltage. The voltage divider is characterized by a precharging transistor included in the voltage divider which has electrical and geometrical characteristics similar to those of the memory cells in such a manner as to adapt the precharging voltage to the characteristics of the cells.

Abstract: The influence of the resistance of the connection between a terminal of voltage limiting diodes against discharges of electrostatic nature which may hit a pad of an integrated circuit and a respective common potential node of the integrated circuit (supply or ground node) is unsuspectably critical. A resistance of just few ohms may depress the maximum tolerable discharge voltage by several thousands volts and the relationship between such two parameters is hyperbolic. Such a critical resistance may advantageously be reduced by utilizing more levels of metallization purposely connected in parallel and/or by "shifting" the protection diodes near the real (and not virtual) common potential node of the circuit or by utilizing "ring" metallizations over different levels for both the common potential nodes of the circuit.

Abstract: This circuit comprises a phase-lock stage receiving at the input a reference signal and the synchronism signal EN and generating at the output a triangular signal in phase correlation with the synchronism signal, a rectangular waveform generator receiving at the input the triangular signal and supplying at the output a rectangular signal, a drive element receiving the rectangular signal and generating a periodic control signal, as well as a phase comparator receiving at the input the triangular signal and the control signal, as well as a further reference signal and generating at the output an error signal correlated with the phase shift of the drive element and fed to the rectangular waveform generator. The reference signal fed to the phase-lock stage or to the phase comparator can be suitably varied within preset limits by an external potentiometer.

Abstract: The memory cell comprises a selection transistor, pickup transistor and a tunnel condenser formed using a single layer of polysilicon. The tunnel condenser is formed on an active area distinct and separate from that of the pickup transistor.

Abstract: Disclosed is an electrically alterable, floating gate type, nonvolatile, semiconductor memory device wherein the gate oxide layer in the "injection" area between the silicon (drain region of the device) and the floating gate has an increased thickness with respect to the thickness of the same gate oxide layer over the channel region of the device in order to decrease the parasitic capacitance of the injection area, thus improving the programming threshold voltage characteristics. A method for fabricating the improved memory device is also disclosed.

Abstract: A power transistor with self-protection against direct secondary breakdown comprises a plurality of elementary transistors having their emitter terminals mutually connected and forming a common emitter terminal, collector terminals also mutually connected and forming a common collector terminal, and base terminals connected to at least one current source. Switches are furthermore provided selectively associated with some of the elementary transistors, preferably with one elementary transistor every two, and allowing operation of the associated elementary transistors in the saturation operating region and switching off the associated elementary transistors during high-voltage operation.