Abstract: An apparatus and method for switching between two power supplies, a primary power supply and a secondary power supply. The present invention generates a first reference voltage using the voltage of the primary power supply and the secondary power supply, wherein the primary power supply voltage is variable. The present invention also generates a second reference voltage based on the voltage of the primary power supply. The first and second reference voltages each have a different slope and the crossing point between these two reference voltages indicate that a switch between the primary power supply and the secondary power supply should occur.

Abstract: An integrated circuit, such as a memory, having an internal data bus for communicating the output of a sense amplifier, is disclosed. The sense amplifiers are of the differential type, having first and second sense nodes at which the amplified differential signal appears. When unselected, or during precharge, each sense amplifier is precharged so that its sense nodes are at a power supply voltage, for example V.sub.cc. Each sense amplifier is connected to a data driver of the push-pull type, in such a manner that both the pull-up and pull-down transistors are off in the precharged or unselected state. This ability to tristate the data driver from the precharged state of the sense amplifier allows for the high impedance state to be entered without requiring an additional signal to be communicated thereto. Such operations as precharging the data bus conductors are thus facilitated, providing improved access time performance.

Abstract: A driver circuit writes data to a memory cell during a write cycle and uncouples the write power terminals from the write terminals during a test mode. The driver circuit includes a first and second data input terminals that typically receive complementary data signals during a write cycle, a test terminal, a write-enable terminal, first and second write power terminals, and first and second write terminals that are coupled to the memory cell. The circuit respectively uncouples the first and second write terminals from the first and second write power terminals when a first signal level, which indicates the test mode, is present on the test terminal. The driver circuit may also couple the first and second write terminals to a reference voltage such as a ground voltage when the first signal level is present on the test terminal.

Abstract: A method for reducing the transient response time of a voltage regulator when the load attached to it is entering or exiting a lower power consumption level by changing the bandwidth of the voltage regulator without compromising its stability, and a bandwidth regulator for implementing such a method are disclosed, wherein the bandwidth of the voltage regulator is changed based on a signal sent by a control device when it senses that the component is about to change power consumption levels.

Abstract: An integrated circuit having a memory array comprised of a plurality of memory cells arranged in rows and columns and a logic circuitry including column decoder and read/write circuitry, wherein each column includes a plurality of memory cells connected in parallel by way of a pair of true and complement bitlines extending from the memory array to the logic circuitry. In order to perform a complete voltage stress test of the memory array, inside the array true and complement bitlines are alternated so that every true bitline is adjacent exclusively to complement bitlines and every complement bitline is adjacent exclusively to true bitlines. According to a first embodiment of the invention, bitlines exiting from the memory array are connected directly to the logic circuitry, while according to a second embodiment, between the array and the logic circuitry, at least one pair of true and complement bitlines is twisted so that one bitline cross over the other.

Abstract: A preslewing circuit to rapidly drop a voltage on the gate of a power device in a power stage has a combination of a bipolar transistor and CMOS transistors. The gate voltage is brought down by the preslewing circuit to a level at which an output voltage can begin to change. The combination has high conduction and can be integrated readily, with good internal isolation, in a small chip area, thus having qualities desirable for high performance, integrated, driver circuits.

Abstract: A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect.

Abstract: A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are provided to expose portions of the pads for testing the device and fusible links. After testing and laser repair, a second passivation layer is formed over the wafer followed a deposit of the protective overcoat. The protective overcoat is patterned and etched, exposing the pads. The remaining portions of the protective overcoat are used as a mask to remove portions of the second passivation layer overlying the pads. Leads are then attached to pads and the devices are encapsulated for packaging. The second passivation layer overlaps edge portions of the first passivation layer at the bond pads to enhance moisture resistance.

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.

Abstract: A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode.

Abstract: A system for packaging integrated circuit components including a ball grid array substrate with a plurality of solder balls coupled to the substrate. A semiconductor device is mounted on the substrate and electrically coupled to the solder balls. One or more terminals are coupled to the substrate and electrically coupled to said semiconductor device. A detachable module contains auxiliary component. The module comprises a body portion for containing the component and one or more electrical connectors for mating with respective terminals to hold the module to the substrate and to electrically couple the component with the semiconductor device. The terminals may also be connected to the solder balls such that a component may be optionally provided either on the circuit board or in the detachable module.

Abstract: A motor drive control circuit for operation in both linear and PWM modes includes a switchably connected compensation network. The compensation network has a capacitor that provides control loop compensation. To avoid transient effects during the settling time upon transitions from one mode to the other, the switch connecting the compensation network in the circuit is closed only during linear operation and not during PWM mode operation. When the switch is open, the capacitor holds a previously attained potential that is reapplied to the circuit when the switch is again closed.

Abstract: A method is provided for forming a landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of conductive regions are formed over a substrate. A polysilicon landing pad is formed over at least one of the plurality of conductive regions. After the polysilicon is patterned and etched to form the landing pad, tungsten is then selectively deposited over the polysilicon to form a composite polysilicon/tungsten landing pad which is a good etch stop, a good barrier to aluminum/silicon interdiffusion and a good conductor.

Abstract: Signal propagation times in circuit paths are matched to compensate for signal delays due to differences in the physical parameters, such as lengths, of the circuit paths. This is accomplished by adjusting the length of lead lines and by the addition of resistors in series with shorter lead lines in a chip or die. In a chip with an active device, such as logic, having multiple input lines, the lines are divided into long lines and short lines. All long lines are laid out so as to have the same length and to use the least amount of chip surface area. Similarly, all short lines are laid out on the chip so as to have the same length while using the least amount of chip surface area. With all the short lines having the same propagation time difference relative to all the long lines, the same resistive element is added to all the short lines to effect the same RC delay in signal propagation on the short lines so as to match the signal propagation time on the short lines with that on the long lines.

Abstract: A charge pump circuit with negative current feed back is disclosed. The charge pump circuit consists of charge pump stages, switch circuits in between the stages, and a feedback loop to control the conductivity of the switch circuit. The conductivity of the switch circuits is controlled by modulating the bias current of the switch circuit which modulates its conductivity. By using the feedback loop to control the conductivity, the output voltage of the charge pump circuit can be regulated.

Abstract: An electrical connection structure is provided for protecting a barrier metal layer within a contact opening during the formation of an aluminum interconnection layer overlying a tungsten plugged connection structure. The deposited tungsten plug overlying the barrier metal layer is etched back sufficiently to create a slight recess at the opening. A thin layer of tungsten is then selectively deposited for filling the recess. This layer acts as an etch stop during aluminum interconnection layer formation and protects the underlying barrier metal layer.

Abstract: An integrated circuit package has leadless solderballs attached to the substrate with a conductive thermoplastic adhesive. The leadless solderballs are preferably made with a copper-nickel-gold alloy. The conductive thermoplastic is preferably of the silver fill type. The integrated circuit package is placed in a frame and held to the printed circuit board with a clamp or with a screw.

Abstract: An integrated circuit package is disclosed, of the type having a pin-fin heat sink attached to the surface. A flat plate is attached to the ends of the pins of the heat sink, to provide a planar surface area of adequate size to allow a vacuum pickup tool to pick and place the packaged integrated circuit, and to receive marking and symbolization.

Abstract: The present invention ensures that the entire data path of the synchronous integrated circuit device composed of master and slave latches is initialized upon power-up in a test mode, thereby overcoming a prior art problem of non-initialization of the device data path. In the test mode, the master clock signal is initialized internally to the synchronous integrated circuit device to allow the master latch to conduct. A clock signal which is a derivative of a master clock signal is controlled to be equal to a first logic state in order to control a slave latch element of the synchronous integrated circuit device to conduct, regardless of the state of the master clock signal. Controlling the clock signal to be equal to the first logic state allows the clock signal to be able to control the slave latch element so that entire data path of the integrated circuit device is initialized upon power-up of the device in the test mode.

Abstract: A circuit and method for testing on-chip memory for a microprocessor or a microcomputer is disclosed. The memory test circuit includes an input register, an output register, an adder, and a sequencer to control the test process. The process includes receiving a simple communication protocol from the control unit to start the test, running a common memory test such as a checker board, AAAAh, 5555h and the like, and then storing the test results in an output register. The test circuit can include a bi-directional RESET signal means for disabling the system while the microprocessor or microcomputer runs its memory test.