Abstract: According to the present invention, a modification of standard successive approximation analog to digital converter circuitry may be utilized to measure an unknown analog value and to produce a digital value after conversion that automatically contains an offset value with respect to a given measurement range. The offset achieved by the successive approximation A/D converter is proportional to an external reference which is used as the reference for the successive approximation A/D converter. The digital value produced according to the present invention is not representative of a raw measurement value but rather is representative of a value with respect to a given measurement range; thus, a digital value of 0 may indicate the minimum value of a given measurement range rather than a value of 0 Ohms, 0 volts, or 0 Amps. This may be expressed in equation form where the desired conversion value is represented by:k(X.sub.unknown -X.sub.offset)where k is a constant, X.sub.

Abstract: A circuit for driving a voice coil motor used to position the heads of a disk drive is disclosed. The circuit consists of a an H-bridge circuit, a controller, and a feedback loop. The feedback loop prevents the BEMF from driving a voltage on the voice coil motor above the supply voltage.

Abstract: An input buffer, for an asynchronous integrated memory circuit incorporating a memory circuit, including a latch circuit controlled by a write enable signal is disclosed. The input stage of the input buffer is connected to a pass gate, which is controlled by the write enable signal so that the pass gate is nonconductive when the write enable signal is active. The output of the pass gate is connected to an input of the latch circuit. The latch circuit is controlled by the write enable signal so that the signal present on the input of the latch is latched when the write enable signal is active. From an output of the latch circuit are obtained true and complementary signals, which are applied to outputs of the buffer circuit. As a result, when the write enable signal is active, the signal present on the input of the buffer is latched and presented to the outputs of the buffer, and the latch circuit is isolated from the input of the buffer until the write cycle is terminated.

Abstract: Circuitry for performing a special test of an integrated memory circuit is disclosed, where the special test requires driving of both bitlines associated with a column of memory cells to a selected logic level, such as ground. The special test is performed in a mode different from normal operation of the memory, and is useful in performing a write disturb test, and in performing stress tests of memory elements such as pass transistors in static random access memory cells. The special test is performed by generating an internal signal selecting the placement of both bitlines in one or more bitline pairs to the selected logic level. Circuitry is also disclosed which uses the output enable terminal, in the special test mode, for controlling the driving of both bitlines to the selected logic level, as the output enable terminal otherwise has no required function in this special test mode.

Abstract: A method is provided for forming a substantially planarized surface of an integrated circuit, and an integrated circuit formed according to the same. A conductive area is formed over a portion of a dielectric region. A first spin-on-glass layer is formed over the conductive area and exposed dielectric region. A second spin-on-glass layer is formed over the first spin-on-glass layer; wherein the second spin-on-glass layer has a slower etch rate than the first spin-on-glass layer. A partial etchback of the first and second spin-on-glass layers is performed forming a substantially planar surface.

Abstract: According to the method of the present invention, stress testing of decoders and other periphery circuits of synchronous RAMs is performed within a reasonable period of time and without an increase in the complexity of stress testing or fabrication of synchronous RAMs. In order to stress test decoders and periphery circuits of a synchronous RAM to obtain maximum fault coverage of possible latent defects, a periphery stress mode is defined through appropriate manipulation of the Power-On Reset signal of the device such that all nodes of a memory array of the synchronous RAM are pulled in the opposite logic state from that required for a memory cell stress mode. In the periphery stress mode, the Power-On Reset signal is allowed to pulse upon power-up of the synchronous RAM device such that latches and flip flops of the device are forced in a logic state that disables all rows and columns of the memory array of the device. Additionally, all D.C.

Abstract: A method and circuit for significantly reducing a delay added to a clock signal which clocks an output of a first circuit into an input of a second circuit in a semiconductor device. An output of a first circuit is connected to a data line. The first circuit is designed with elements having a selected set of design parameters, such as transistor dimensions and transistor orientation. A second circuit is connected to the data line and also receives a clock signal generated by a signal delay circuit. The signal delay circuit receives an output enable signal, and after a delay period, produces the clock signal in response to the output enable signal. At least a portion of the signal delay circuit utilizes elements having the selected set of design parameters utilized in the first circuit.

Abstract: An integrated circuit with an integer odd number C of electrical contacts, wherein each of the electrical contacts is for communicating a data value. The integrated circuit also includes four memory arrays for storing data. The first and third memory arrays are operable to simultaneously output an integer even number E of data values. The second and fourth memory arrays are operable to simultaneously output an integer odd number D of data values. The integrated circuit further includes circuitry for selectively coupling the first, second, third, and fourth memory arrays to the electrical contacts, wherein the circuitry for selectively coupling is operable to couple the first and fourth memory arrays to the electrical contacts in a first state so that the first memory array outputs E data values and the fourth memory array outputs D data values in the first state.

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.

Abstract: A read circuit for a memory cell includes a sense amplifier and an equilibrate circuit. The sense amplifier is coupled to the memory cell via a pair of data lines, and amplifies the data signals that the memory cell provides. The equilibrate circuit is coupled to the sense amplifier, receives an equilibrate signal, and, when the equilibrate signal has an active level, equilibrates the sense amplifier. When the equilibrate signal has an inactive level, the equilibrate circuit causes the sense amplifier to draw substantially zero supply current, regardless of the levels of any signals on the data lines. The read circuit may also include an enable circuit that receives an enable signal and is coupled to the sense amplifier. When the enable signal has an active level, the enable circuit allows the sense amplifier to amplify the data signals on the data lines. When the enable signal has an inactive level, the enable circuit prohibits the sense amplifier from amplifying the data signals on the data lines.

Abstract: A method and circuit for braking a forward rotation of a rotor of a polyphase DC motor. A commutation sequencer is incremented by several phases to produce an incremented commutation sequence to produce a magnetic flux vector that lags a magnetic pole of the motor. Driving currents are applied to coils of the motor in accordance with the incremented commutation sequence to brake the rotor. The method is implemented in a circuit that has a sequencer for incrementally generating sets of commutation signals to select stator coils for energization to rotate the rotor. A power stage to which the commutation signals are applied energizes the selected coils in accordance with the commutation signals. A circuit interrupts the energization of the selected coils and the commutation sequence is altered to produce a sequence that produces a negative torque on the rotor.

Abstract: The time required to output data from an output buffer is significantly reduced by having a slave latch in a parallel connection with a master latch. Incoming data is stored in a master latch on a first phase of a clock pulse. On the second phase of the clock pulse, the data is output of the master latch and provided to an output driver. A slave latch is coupled to the input node of the output driver. On the subsequent phase of the clock, the slave latch is switched on to hold the state of the input to the output driver constant. The slave latch thus receives the output of the master register in parallel with the output driver and also performs its function of maintaining the input to the output buffer for one entire clock pulse while new data is being presented to the master latch. Data is thus provided more quickly to the output driver than was previously possible with prior art master/slave configurations.

Abstract: A circuit and related method are provided for parallel stressing of a plurality of memory circuits integrated on dies on a silicon wafer. On each die, a test mode control circuit, having a first and a second test mode control inputs, and a test enable circuit, having a first and a second test enable inputs, are used to enable test operation mode and to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the memory cells. Contemporaneously are also exercised entire paths of buffers. The silicon wafer is then heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible to stress test for ionic contamination, trap sites and weak oxides a plurality of integrated circuits on the same wafer in a short time, requiring only a limited number of test signals.

Abstract: A circuit and method for an integrated multifunction voltage regulator is disclosed. The integrated circuit features a voltage preregulator having a battery input and a Vcc output, a voltage bus for distributing the Vcc voltage, and a plurality of function blocks which are connected to the Vcc buss and are driven by the Vcc voltage. The function blocks include voltage regulators, protected battery switches, band gap voltage references, and reset circuits.

Abstract: A method and apparatus for switching a motor between bipolar and unipolar mode. During each phase of the bipolar mode, one of the coils floats and has a back emf. In the method, first, a mode change signal requesting a change between the bipolar mode and the unipolar mode is received. Second, the back emf across the floating coil is monitored. Third, a point in time when the back emf equals the center tap voltage is detected. Last, the motor is switched between the bipolar mode and the unipolar mode at a point away from point in time when the back emf across the floating coil equals the center tap voltage. Various circuitry is also disclosed for switching a motor between a bipolar mode and a unipolar mode.

Abstract: A stator coil driver circuit for a brushless DC motor, which minimizes torque ripple by keeping the current in the commutating phases constant, is disclosed. The circuit includes a slew rate control circuit for ramping up the current or ramping down the current during commutation. The slew rate control circuit consists of a capacitor, a first current source for charging the capacitor, and a second current source for discharging the capacitor. The circuit also includes a sense resistor or a sensefet and an operational transconductance amplifier for providing feedback control.

Abstract: According to the present invention, standard analog to digital converter circuitry may be utilized to measure an unknown analog value and to produce a digital value after conversion that automatically contains an offset value with respect to a given measurement range. The digital value produced according to the present invention is not representative of a raw measurement value but rather is representative of a value with respect to a given measurement range; thus, a digital value of 0 may indicate the minimum value of a given measurement range rather than a value of 0 Ohms, 0 volts, or 0 Amps. This may be expressed in equation form where the desired conversion value is represented by:k(X.sub.unknown -X.sub.offset)where k is a constant, X.sub.unknown is the unknown analog value being measured, and X.sub.offset is the offset value. X.sub.offset the offset value may or may not be equal to a reference value.

Abstract: A redundancy structure having fewer pass gates in the redundant decoder for quicker access to a redundant columns and a reduction in the complexity of the redundancy structure.

Abstract: A plurality of bit lines is arranged in columns and grouped into a first set of bit lines and a second set of bit lines. Each bit line in the first set of bit lines alternates with each bit line in the second set of bit lines. First switching means electrically connects the first set of bit lines to a first voltage level and, simultaneously, second switching means connects the second set of bit lines to a second voltage level. This permits a bit line stress test that will reveal defects or failures in a memory chip.

Abstract: A system for packaging circuit components is disclosed. The system includes a substrate having a plurality of openings to accommodate mounting various circuit components and the circuit components mounted therein. The substrate has first, second, third and fourth contacts providing mechanical and electrical connection to the various components. An opening is provided for accommodating a first auxiliary component such as a battery wherein the battery terminals attach to the first and second contacts. Another opening is provided in the substrate to accommodate a second auxiliary component such as a crystal resonator having leads which attach to the third and fourth contacts. The substrate preferably has another opening for accommodating an integrated circuit chip package, the chip package having conventional leads for mounting to a circuit board and terminals for connecting to the substrate contacts.