Abstract: A stator coil driver circuit for a brushless DC motor, with an improved current mirror, is disclosed. The improved current mirror has a first transistor which conducts current and a second transistor configured to mirror the current of the first transistor. Additionally, the improved mirror circuit includes a unity gain amplifier connected in between the gates of the first and second transistor. The effect of the unity gain transistor is to provide for a faster turn-off of the second transistor and reduce oscillation of the circuit.

Abstract: A comparator with hysteresis which has a bias current circuit, a differential input stage, and an output stage is disclosed. The differential input stage uses an analog switch to connect the body of a field effect transistors to either a first voltage or a second voltage. The analog switch in the preferred embodiment is a double-throw switch.

Abstract: According to the present invention, column redundancy circuitry provides column redundancy to an integrated circuit memory device having a multiple block memory architecture with limited programming overhead and maximum flexibility. Column redundancy circuitry is placed within a block of the multiple block memory architecture and may be placed within multiple blocks of the integrated circuit device as required. The column redundancy circuitry has a column select multiplexing circuit, an input/output select circuit for a redundant column of the memory array, and a redundant column select circuit to drive the input/output select circuit for a redundant column. Fuse circuitry contained within column select multiplexing circuit disables a bad prime column by removing fuses in order to isolate the bitline pair associated with the bad column from the read and write busses of the memory array.

Abstract: A method for forming a contact via in an integrated circuit includes the formation of an aluminum conductive element on an integrated circuit device. A conformal insulating layer is then deposited over the device. Using a masking layer, an anisotropic etch is performed to open a via through the conformal insulating layer. During the anisotropic etch, polymers are created from the resist and etch chemistry and adhere to the sidewalls of the via. A resist developer containing Tetra Methyl Amonium Hydroxide is used to remove the polymers from the via. A contact may now be formed by depositing conductive material into the via.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: A structure and method for fabricating intergrated circuit which provides for the detection of residual conductive material. A first conductive layer is deposited over the intergrated circuit and patterned to define a first interconnect layer. An insulating layer in then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during pattering of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.

Abstract: A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region.

Abstract: A structure and method for forming contact structures in integrated circuits. A buffer layer is formed over an underlying conductive element. A first conductive layer is then deposited over the buffer layer and patterned to define a first interconnect layer. While the first interconnect layer is patterned, the buffer layer protects the underlying conductive element from damage. Portions of the buffer layer which are not covered by the first interconnect layer are then removed, and a second conductive layer is deposited over the integrated circuit. The second conductive layer is then anisotropically etched to form conductive sidewall spacers alongside the vertical sidewalls of the first interconnect layer, where at least one of the conductive sidewall spacers makes electrical contact with the underlying conductive element. Therefore, a conductive contact is made between the underlying conductive element and the first interconnect layer through at least one of the conductive sidewall spacers.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: An integrated circuit structure contains both highly resistive regions and highly conductive interconnect regions in a single layer of polycrystalline silicon. The resistive regions have a smaller cross section than the interconnect regions as a result of partial oxidation. Their thickness and width are reduced from that of the interconnect regions. The partial oxidation leaves an oxide region, derived from polycrystalline silicon, on both the top and sides of the resistive regions.

Abstract: The invention is used in a disk drive and comprises a feedforward circuit connected between the head position circuit and the speed control loop circuit. The feedforward circuit precompensates the speed control loop for changes in rotation drag due to movements in the head of a disk drive. The feedforward circuit may include one or more deadband amplifiers and may include filter circuit. The invention disclose the method for controlling the speed of a spindle motor in a disk drive which includes the step of precompensating the speed control loop circuit with a processed head positioning signal.

Abstract: A vertical switched-emitter device structure in which the body of vertical-current-flow MOS device is formed in a P-type surface epi region, and dielectric isolation laterally separates the body from the surface contact to the buried P-type base region.

Abstract: A dam is provided on a surface of a circuit board to which an integrated circuit device is to be mounted. The dam defines a region between the integrated circuit package and the circuit board, and a material is injected into this region after the device has been mounted on the circuit board. This material preferably is a good thermal conductor, assisting in the removal of heat from the device. The injected material also preferably acts as an adhesive, more firmly bonding the device the circuit board.

Abstract: A circuit and related method are provided internally to an integrated circuit for stress testing its memory. A test mode control circuit, having a first and a second test mode control input, is used, during special test operation mode, to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the array of memory cells. Contemporaneously are also exercised entire paths of buffers. The integrated circuit is heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible, at wafer level, to stress test for ionic contamination, trap sites and weak oxides the integrated circuit in a short time, requiring only a limited number of test signals.

Abstract: A method is provided for forming a polysilicon buried contact of an integrated circuit, and an integrated circuit formed according to the same. A field oxide region is formed over a portion of a substrate leaving an exposed active region. An oxide layer is formed over the active region. A first photoresist layer is formed and patterned over the first silicon layer. The first silicon layer is then etched to form an opening therethrough to expose a portion of the oxide layer. The oxide layer is etched through the opening to expose a portion of the substrate. A conductive etch stop layer is formed over the exposed portion of the substrate and the first photoresist layer. The first photoresist layer and the etch stop layer overlying the first photoresist layer are then removed. A second silicon layer is formed over the first silicon layer and the remaining etch stop layer. A second photoresist layer is formed and patterned over the second silicon layer.

Abstract: According to the present invention, an integrated circuit device is capable of responding to more than one input threshold voltage level by making only minimal changes to the device. The input buffer of the integrated circuit device is modified to be a programmable buffer that is controlled by a control input signal which may be generated by several different control means. Such control means include a bond option, a mask option, a fuse option, a register option, and a voltage detector option.

Abstract: Local interconnect structures and processes using dual-doped polysilicon. A single implant dopes part of the polysilicon local interconnect layer p-type, and also diffuses through the polysilicon interconnect layer to enhance the doping of the PMOS drain regions, and also (optionally) adds to the doping of the PMOS source regions to provide source/drain asymmetry. The polysilicon interconnect layer is clad to reduce its conductivity, optionally with patterned rather than global cladding so that the diode can be used as a load element if desired.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: A dual-port data cache is provided having one port dedicated to servicing a local processor and a second port dedicated to servicing a system. The dual-port data cache is also capable of a high speed transfer of a line or lines of entries by placing the dual-port data cache in "burst mode." Burst mode may be utilized with either a read or a write operation. An initial address is latched internally, and a word line in the memory array is activated during the entire data transfer. A control circuit is utilized to cycle through and access a number of column addresses without having to provide a separate address for each operation.