Abstract: A method of manufacturing non-photosensitive polyimide passivation layer is disclosed. The method includes: spin-coating a non-photosensitive polyimide layer over a wafer and baking it; depositing a silicon dioxide thin film thereon; spin-coating a photoresist layer over the silicon dioxide thin film and baking it; exposing and developing the photoresist layer to form a photoresist pattern; etching the silicon dioxide thin film by using the photoresist pattern as a mask; removing the patterned photoresist layer; dry etching the non-photosensitive polyimide layer by using the patterned silicon dioxide thin film as a mask; removing the patterned silicon dioxide thin film; and curing to form a imidized polyimide passivation layer. The method addresses issues of the traditional non-photosensitive polyimide process, including aluminum corrosion by developer, tapered profile of non-photosensitive polyimide layer and generation of photoresist residues.

Abstract: A decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage.

Abstract: A stacked inductor with different metal thickness and metal width. The stacked inductor comprises top and bottom metal traces which are aligned with each other. The thickness and width of the top and bottom metal traces are different. The top and bottom metal traces are connected at the end of metal trace with via holes. The inductance is increased with the use of the mutual inductance between top and bottom metal layers The parasitic resistor is reduced due to the difference of the top and bottom metal widths.

Abstract: The present invention discloses a method of manufacturing superjunction structure, which comprises: step 1, grow an N type epitaxial layer on a substrate having a (100) or (110) oriented surface; step 2, etch the N type epitaxial layer to form trenches therein; step 3, fill the trenches by P type epitaxial growth in the trenches by using a mixture of silicon source gas, halide gas, hydrogen gas, and doping gas. By using the manufacturing method according to the present invention, no void or only small voids are formed in the trenches after trench filling.

Abstract: A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, which includes: two isolation structures each being formed in a trench; a set of three or more pseudo buried layers formed under each trench with every adjacent two pseudo buried layers of the set being vertically contacted with each other; and a collector region. In this design, the lowermost pseudo buried layers of the two sets are laterally in contact with each other, and the collector region is surrounded by the two isolation structures and the two sets of pseudo buried layers. As the breakdown voltage of a SiGe HBT according to the present invention is determined by the distance between an uppermost pseudo buried layer and the edge of an active region, SiGe HBTs having different breakdown voltages can be achieved. A manufacturing method of the SiGe HBT is also disclosed.

Abstract: A structure for picking up a buried layer is disclosed. The buried layer is formed in a substrate and has an epitaxial layer formed thereon. One or more isolation regions are formed in the epitaxial layer. The structure for picking up the buried layer includes a contact-hole electrode formed in each of the isolation regions. A bottom of the contact-hole electrode is in contact with the buried layer. As the structure of the present invention is formed in the isolation region without occupying any portion of the active region, its size is much smaller than that of a sinker region of the prior art. Therefore, device area is tremendously reduced. Moreover, as the contact-hole electrode picks up the buried layer by a metal contact, the series resistance of the device can be greatly reduced. A method of forming the above structure is also disclosed.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) having a deep pseudo buried layer is disclosed. The SiGe HBT includes isolation structures formed in trenches, first pseudo buried layers and second pseudo buried layers, and a collector region. The first pseudo buried layers are formed under the respective trenches and the second pseudo buried layers are formed under the first pseudo buried layers, with each first pseudo buried layer vertically contacting with a second pseudo buried layer. The second pseudo buried layers are laterally connected to each other, and the collector region is surrounded by the trenches, the first pseudo buried layers and the second pseudo buried layers. The cross section of each of the trenches has a regular trapezoidal shape, namely, each trench's width of its top is smaller than that of its bottom. A manufacturing method of the SiGe HBT is also disclosed.

Abstract: A PIS capacitor in a SiGe HBT process is disclosed, wherein the PIS capacitor includes: a silicon substrate; a P-well and shallow trench isolations formed in the silicon substrate; a P-type heavily doped region formed in an upper portion of the P-well; an oxide layer and a SiGe epitaxial layer formed above the P-type heavily doped region; spacers formed on sidewalls of the oxide layer and the SiGe epitaxial layer; and contact holes for picking up the P-well and the SiGe epitaxial layer and connecting each of the P-well and the SiGe epitaxial layer to a metal wire. A method of manufacturing the PIS capacitor is also disclosed. The PIS capacitor of the present invention is manufactured by using SiGe HBT process, thus providing one more device option for the SiGe HBT process.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, in which a shallow trench is formed of a first shallow trench and a second shallow trench vertically joined together in the active region, the second shallow trench being located directly under the first shallow trench and having a width less than that of the first shallow trench; a pseudo buried layer is formed surrounding the bottom and side walls of the second shallow trench and is in contact with the collector region to serve as a connection layer of a collector; a deep hole contact is formed in the shallow trench and is in contact with the pseudo buried layer to pick up the collector. A SiGe HBT manufacturing method is also disclosed. The present invention is capable of improving the cut-off frequency of a SiGe HBT.

Abstract: A bipolar transistor is disclosed, which includes a collector region, a base region, an emitter region and field plates. Each field plate is present in a structure of a flat sidewall covering one side face of the active region so that it also covers the collector region from one side. The field plate has its surface parallel to the side face of the active region and is isolated from the side face of the active region by a pad oxide layer. The field plate has its top lower than the surface of the active region. The bipolar transistor is capable of improving the breakdown voltage of the device without increasing the collector resistance or deteriorating the frequency characteristic. A method of manufacturing bipolar transistor is also disclosed.

Abstract: A method of inserting dummy patterns is provided. The method includes: determining an applicable area in which dummy patterns shall be inserted and an inapplicable area in which dummy patterns shall not be inserted on a chip; and inserting dummy patterns starting from one side of the inapplicable area and arranging the inserted dummy patterns into circles. The method of the present invention ensures that dummy patters are preferentially inserted around the device that requires protection by dummy patterns, so that good uniformity of chip pattern densities is guaranteed and within-wafer uniformity is improved, thus improving the yield and performance of semiconductor devices.

Abstract: A SiGe HBT having a position controlled emitter-base junction is disclosed. The SiGe HBT includes: a collector region formed of an N-doped active region; a base region formed on the collector region and including a base epitaxial layer, the base epitaxial layer including a SiGe layer and a capping layer formed thereon, the SiGe layer being formed of a SiGe epitaxial layer doped with a P-type impurity, the capping layer being doped with an N-type impurity; and an emitter region formed on the base region, the emitter region being formed of polysilicon. By optimizing the distribution of impurities doped in the base region, a controllable position of the emitter-base junction and adjustability of the reverse withstanding voltage thereof can be achieved, and thereby increasing the stability of the process and improving the uniformity within wafer.

Abstract: A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance.

Abstract: This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost.

Abstract: This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process.

Abstract: A superjunction structure with unevenly doped P-type pillars (4) and N-type pillars (2a) is disclosed. The N-type pillars (2a) have uneven impurity concentrations in the vertical direction and the P-type pillars (4) have two or more impurity concentrations distributed both in the vertical and lateral directions to ensure that the total quantity of P-type impurities in the P-type pillars (4) close to the substrate (8) is less than that of N-type impurities in the N-type pillars close to the substrate; the total quantity of P-type impurities in the P-type pillars close to the top of the device is greater than that of N-type impurities in the N-type pillars close to the top. A superjunction MOS transistor and manufacturing method of the same are also disclosed. The superjunction structure can improve the capability of sustaining current-surge of a device without affecting or may even reduce the on-resistance of the device.

Abstract: A bond pad structure for an integrated circuit chip package is disclosed. The bond pad structure includes a top metal layer, a patterned metal layer and an interconnection structure. The patterned metal layer is formed below the top metal layer and includes an annular metal layer and a plurality of metal blocks evenly arranged at a central area of the annular metal layer; the patterned metal layer is connected to the top metal layer through both the annular metal layer and the metal blocks. The interconnection structure is formed below the patterned metal layer and is connected to patterned metal layer only through the annular metal layer. By using the above structure, active or passive devices can be disposed under the bond pad structure and will not be damaged by package stress. An integrated circuit employing the above bond pad structure is also disclosed.

Abstract: A vertical PNP device in a silicon-germanium (SiGe) BiCMOS process is disclosed. The device is formed in a deep N-well and includes a collector region, a base region and an emitter region. The collector region has a two-dimensional L-shaped structure composed of a lightly doped first P-type ion implantation region and a heavily doped second P-type ion implantation region. The collector region is picked up by P-type pseudo buried layers formed at bottom of the shallow trench field oxide regions. A manufacturing method of vertical PNP device in a SiGe BiCMOS process is also disclosed. The method is compatible with the manufacturing processes of a SiGe heterojunction bipolar transistor in the SiGe BiCMOS process.

Abstract: A SiGe HBT is disclosed. A collector region consists of a first ion implantation region in an active area as well as second and third ion implantation regions respectively at bottom of field oxide regions. Each third ion implantation region has a width smaller than that of the field oxide region, has one side connected to first ion implantation region and has second side connected to a pseudo buried layer; each second ion implantation region located at bottom of the third ion implantation region and pseudo buried layer is connected to them and has a width equal to that of the field oxide region. Third ion implantation region has a higher doping concentration and a smaller junction depth than those of first and second ion implantation regions. Deep hole contacts are formed on top of pseudo buried layers in field oxide regions to pick up collector region.