Abstract: An automatic overclocking controller based on circuit delay measurement is provided, including a central processing unit (CPU), a clock generator, and a timing delay monitor (TDM) controller. Compared with the prior art, the present disclosure has following innovative points: A two-dimension-multi-frame fusion (2D-MFF) technology is used to process a sampling result, to eliminate sampling noise, and an automatic overclocking controller running on a heterogeneous field programmable gate array (FPGA) can automatically search for a highest frequency at which an accelerator can operate safely.

Abstract: The present application provides a method for detecting infertile spermatozoa in a sample, the method comprising: detecting a concentration of at least one metal in the sample that falls outside of a predetermined range using single cell inductively coupled plasma mass spectrometry (sc-ICP-MS). It also provides a method for detecting infertile spermatozoa in a sample, which comprising: detecting a dynamic or kinetic parameter of a signal spike of at least one metal selected from the group of several metallic elements by sc-ICP-MS.

Abstract: An energy-efficient memory for cryogenic computing is provided. The energy-efficient memory includes a plurality of memory banks, where each of the memory banks includes a cryogenic semi-static, dual-port, boost-free gain cell (CSDB-GC) macro module, a universal address decoder, and a different address decoder. The CSDB-GC macro module includes a plurality of columns of local blocks, and each of the local blocks includes a plurality of CSDB-GC memory cells. A final measurement result of a 16 Kb CSDB-eDRAM shows that the 16 Kb CSDB-eDRAM achieves data retention time (DRT) of 16.67 seconds, which is 2.6 times longer than DRT of a state-of-the-art cryogenic eDRAM at a temperature of 4.2 K, and achieves lower refresh power (0.11 pW/Kb). In addition, the 16 Kb CSDB-eDRAM also achieves shorter access time, namely, 710 ps (1.41 GHz). Compared with the state-of-the-art work, the 16 Kb CSDB-eDRAM has a lowest dynamic power consumption overhead, namely, 49.23 uW/Kb.

Abstract: A dual-six-transistor (D6T) in-memory computing (IMC) accelerator supporting always-linear discharge and reducing digital steps is provided. In the IMC accelerator, three effective techniques are proposed: (1) A D6T bitcell can reliably run at 0.4 V and enter a standby mode at 0.26 V, to support parallel processing of dual decoupled ports. (2) An always-linear discharge and convolution mechanism (ALDCM) not only reduces a voltage of a bit line (BL), but also keeps linear calculation throughout an entire voltage range of the BL. (3) A bypass of a bias voltage time converter (BVTC) reduces digital steps, but still keeps high energy efficiency and computing density at a low voltage. A measurement result of the IMC accelerator shows that the IMC accelerator achieves an average energy efficiency of 8918 TOPS/W (8b×8b), and an average computing density of 38.6 TOPS/mm2 (8b×8b) in a 55 nm CMOS technology.

Abstract: An efficient K-nearest neighbor (KNN) method for a single-frame point cloud of a LiDAR and an application of the efficient KNN method for the single-frame point cloud of the LiDAR are provided, where the efficient KNN method for the single-frame point cloud of the LiDAR is accelerated by a field-programmable gate array (FPGA). In the efficient KNN method for the single-frame point cloud of the LiDAR, a data structure is established based on point cloud projection and a distance scale. The data structure ensures that adjacent points in space are organized in adjacent memories. A new data structure is efficiently constructed. An efficient nearest point search mode is provided.

Abstract: A high-efficient quantization method for a deep probabilistic network achieves good result through hybrid quantization, structure reformulation, and type optimization. Firstly, for a directed acyclic graph (DAG) structure, all nodes in the DAG are clustered, and each node is quantized by a specific arithmetic type based on the clustering category, to obtain a preliminarily quantized deep probabilistic network. Secondly, the multi-in nodes in a preliminarily quantized deep probabilistic network are reformulated based on the input weights, structural reformulation converts a multi-in node into a binary tree network containing only two-input nodes, and parametrical reformulation is performed on the reformulated structure. Finally, arithmetic types of all nodes are optimized by using an arithmetic type search method based on power consumption analysis and network accuracy analysis.

Abstract: An energy-efficient cryogenic-in-memory-computing (CIMC) accelerator includes cryogenic 3T (C3T) macros. Each of the C3T macros comprises a C3T array containing M rows×N columns of bitcells. An input signal is converted into a timing sequence signal of a corresponding pulse width by using a digital timing sequence converter array. A C3T bitcell of a corresponding row in the C3T macro is controlled to perform charging and discharging on a read bit line (RBL) of a corresponding column. A voltage on the RBL of the corresponding column is sampled by a sense amplifier configured in each C3T macro to obtain a final result. With adaptive reference voltage configuration and storage on the chip, this design can achieve fast and low-power boolean/convolutional computing.

Abstract: An additive manufacturing method for fabricating 3D nanostructures is provided, charged species dispersed in a fluid are precisely arranged at nanoscale in each dimension with a configured electric field, so that the charged species are printed on a substrate to form an array of 3D nanostructures as desired. The additive manufacturing method of the present disclosure can be carried out at room temperature and atmospheric pressure without the aid of chemical reaction, laser sources, ion/electron beams, or photosensitive materials, and enables low-cost, ultra-fast printing speed, large-area, high-purity, multi-material, ultra-high-resolution and solves problems encountered in other nanofabrication techniques in making 3D nanostructures, such as a limited range of available printing materials, low resolution, slow printing speed, and one by one serial printing.

Abstract: An ultra-low-voltage static random access memory (SRAM) cell for eliminating half-select-disturbance under a bit interleaving structure includes a cross-coupled inverter pair, two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and two N-type transistors NM3 and NM4, where the two N-type transistors NM3 and NM4 form a readout path. The present disclosure can be applied to applications with a storage requirement at an ultra-low voltage, especially applications with certain requirements for an access speed and reliability of an SRAM at a low voltage. Compared with other different SRAM cells, the ultra-low-voltage SRAM cell can achieve higher read and write working frequencies with similar energy consumptions.

Abstract: A global registration method based on spherical harmonic transformation (SHT) and iterative optimization is provided. Two assumptions are provided: firstly, it is predefined that a minimum percentage of a correct matching pair in an input point cloud is represented as a limit on a quantity of outliers in the point cloud, and secondly, a distance threshold used to determine the correct matching pair is preset based on a scenario and represented as a limited distance of an outlier in the point cloud. In the algorithm provided, the point cloud first undergoes coarse registration to obtain a plurality of search domains, and the search domains are sorted based on an evaluation criterion. A branch and bound method is used to exclude an incorrect search domain and obtain a final registration result.

Abstract: A novel neural modeling framework Neural Transient Field (NeTF) is provided for non-line-of-sight (NLOS) imaging. NeTF recovers the 5D transient function in both spatial location and direction, and the training data input is parametrized on the spherical wave-fronts. A Markov chain Monte Carlo (MCMC) algorithm is used to account for sparse and unbalanced sampling in NeTF.

Abstract: Liquid-liquid phase separation (LLPS) driven protein-based underwater adhesive coatings are made from a dimeric protein comprising a marine adhesive protein (MAP) domain and a liquid-liquid phase separation-mediating low complexity (LC) domain.

Abstract: A computer-implemented method is provided. The method includes obtaining a plurality of images representing projections of an object placed in a plurality of poses and a plurality of translations; assigning a pose embedding vector, a flow embedding vector and a contrast transfer function (CTF) embedding vector to each image; encoding, by a computer device, a machine learning model comprising a pose network, a flow network, a density network and a CTF network; training the machine learning model using the plurality of images; and reconstructing a 3D structure of the object based on the trained machine learning module.

Abstract: A deep neural network based hair rendering system is presented to model high frequency component of furry objects. Compared with existing approaches, the present method can generate photo-realistic rendering results. An acceleration method is applied in our framework, which can speed up training and rendering processes. In addition, a patch-based training scheme is introduced, which significantly increases the quality of outputs and preserves high frequency details.

Abstract: A layout method for a scalable multi-die network-on-chip FPGA architecture is provided. An application of the aforementioned layout method for the scalable multi-die network-on-chip FPGA architecture is further provided. A scalable multi-die FPGA architecture based on network-on-chip and a corresponding hierarchical recursive layout algorithm are provided, aiming to directly map a register transfer level dataflow design generated by existing high-level synthesis onto the provided interconnection architecture. The layout method can exploit the potential for hierarchical topology and make more efficient use of dedicated interconnection resources, such as cross-die nets, network-on-chips, and high-speed transceivers.

Abstract: A material fabrication method comprises (a) fabricating a structure from a programmable amyloid material (PAM) ink comprising an amyloid monomer stabilized in a liquid solvent; and (b) contacting the structure with an agent which triggers polymerization of the amyloid monomer and stabilization of the structure.

Abstract: A dual-six-transistor (D6T) in-memory computing (IMC) accelerator supporting always-linear discharge and reducing digital steps is provided. In the IMC accelerator, three effective techniques are proposed: (1) A D6T bitcell can reliably run at 0.4 V and enter a standby mode at 0.26 V, to support parallel processing of dual decoupled ports. (2) An always-linear discharge and convolution mechanism (ALDCM) not only reduces a voltage of a bit line (BL), but also keeps linear calculation throughout an entire voltage range of the BL. (3) A bypass of a bias voltage time converter (BVTC) reduces digital steps, but still keeps high energy efficiency and computing density at a low voltage. A measurement result of the IMC accelerator shows that the IMC accelerator achieves an average energy efficiency of 8918 TOPS/W (8b×8b), and an average computing density of 38.6 TOPS/mm2 (8b×8b) in a 55 nm CMOS technology.

Abstract: An energy-efficient point cloud feature extraction method based on a field-programmable gate array (FPGA) is mapped onto the FPGA for running. The energy-efficient point cloud feature extraction method based on the FPGA is applied to point cloud feature extraction in unmanned driving; or an intelligent robot. Compared with an existing technical solution, the energy-efficient point cloud feature extraction method based on the FPGA has following innovative points: a low-complexity projection method for organizing unordered and sparse point clouds, a high-parallel method for extracting a coarse-grained feature point, and a high-parallel method for selecting a fine-grained feature point.

Abstract: The present disclosure relates to an in-situ temperature control platform, including an independent sample holder, a sample holder fixing cartridge, a customized sample stage and an anode contact pin. The independent sample holder includes a sample loading spot and a sample holder grip. The sample holder fixing cartridge includes a fixing cartridge body, the fixing cartridge body is provided with a sample holder slot, the bottom surface of the sample holder slot is provided with a heating element slot, and the sample holder slot is aligned with the sample loading spot. The bottom surface of the heating element slot is provided with a heating element fixing pinhole. The customized sample stage includes a sample stage body, the sample stage body is provided with a heating element support, and the heating element support is provided with a heating element.

Abstract: A max-flow/min-cut solution algorithm for early terminating a push-relabel algorithm is provided. The max-flow/min-cut solution algorithm is used for an application that does not require an exact maximum flow, and includes: defining an early termination condition of the push-relabel algorithm by a separation condition and a stable condition; determining that the separation condition is satisfied if there is no source node s, s?S, in the set T at any time in an operation process of the push-relabel algorithm; determining that the stable condition is satisfied if there is no active node in the set T; and terminating the push-relabel algorithm if both the separation condition and the stability condition are satisfied. The early termination technique is proposed to greatly reduce redundant computations and ensure that the algorithm terminates correctly in all cases.