Patents Assigned to Sharp Kabushiki
  • Publication number: 20050223012
    Abstract: In a document management system, a document management server storing in its data storage portion a document management means, document files, and an entry operator list linking thereto; a computer; and a printer are connected via a communications line. The entry operator list is arranged such that a condition for “trial printing” and a maximum number of “official printouts” can be specified. If the content stored in the entry operator list indicates that even one entry operator has not completed entry, then the document management means sets a condition for “trial printing” in a printer driver, whereas if the content stored in the entry operator list indicates that all entry operators have competed entry, then the document management means stores in the entry operator list a number of “official printouts” set and printed by the printer driver, and prohibits printing which exceeds a cumulative number of “official printouts”.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 6, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Takayoshi Ohkohchi
  • Publication number: 20050217798
    Abstract: The plasma processing apparatus includes main electrodes 5, 31 opposed to each other with a plasma processing space 15 interposed therebetween. The plasma processing apparatus further has a side electrode 6 opposed to side faces 5B-1, 5B-2 of the main electrode 5, as well as a side electrode 32 opposed to side faces 31B-1, 31B-2 of the main electrode 31. Therefore, in addition to the plasma processing space 15 between the main electrode 5 and the main electrode 31, an electric field can be formed in spaces between the side faces of the main electrodes 5, 31 and the side electrodes 6, 32, the spaces serving as predischarge areas 16-1, 16-2. By this electric field, processing gas present in the predischarge areas 16-1, 16-2 can be transformed into plasma. Electrons and excitation species of the plasma generated in these predischarge areas 16-1, 16-2 can be supplied directly to the plasma processing space 15.
    Type: Application
    Filed: March 22, 2005
    Publication date: October 6, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Akira Sugiyama, Shuhichi Kitamura, Koji Murakami, Daisuke Takahashi, Shohzoh Yoshimoto
  • Publication number: 20050220350
    Abstract: An image processing apparatus comprises a first color signal detection section of detecting a first color signal indicating a color component of a pixel of interest from the pixel of interest, a second color signal detection section of detecting a plurality of second color signals indicating color components of a plurality of neighbor pixels located in a vicinity of the pixel of interest from the plurality of neighbor pixels, and a direction detection section of detecting a direction of an edge in the vicinity of the pixel of interest based on the first color signal and the plurality of second color signals. The color components of the plurality of neighbor pixels include at least three color components.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 6, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Takashi Morisue
  • Publication number: 20050219611
    Abstract: A data processing apparatus receives and stores data, and then performs processing such as the output of the stored data. The data processing apparatus nullifies already-processed data by means of deletion or overwrite. The data processing apparatus displays a reception screen for receiving from a user a priority instruction for either a processing-speed oriented priority where priority is imparted to the processing of data or a security oriented priority where priority is imparted to the nullification of data. When the security oriented priority is instructed, the data processing apparatus performs the nullification of data immediately after the processing of the data. When the processing-speed oriented priority is instructed, the data processing apparatus performs with priority the processing of data. Then, when not-yet-processed data has been completed, or alternatively after a user has left the site, the data processing apparatus performs the nullification of already-processed data.
    Type: Application
    Filed: March 11, 2005
    Publication date: October 6, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Michihiro Yamashita, Norichika Katsura
  • Publication number: 20050220503
    Abstract: A developing device includes an endless belt stretched around a plurality of support members, a portion of a peripheral surface of the endless belt contacting a portion of a surface of an image carrying member at a contact region, the endless belt being rotated by a driving force transmitted from a driving device at a driving transmission position, and a layer regulating member pressed against a portion of the endless belt at a pressure contact region positioned upstream, with respect to the endless belt's rotation direction, from the contact region. Further provided is a load device applying, to at least a portion of the endless belt between the pressure contact region and the contact region, which is positioned upstream, with respect to the endless belt's rotation direction, from the driving transmission position, a load acting in a direction opposite to the rotation direction of the endless belt.
    Type: Application
    Filed: March 25, 2005
    Publication date: October 6, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Kenji Asakura
  • Publication number: 20050219180
    Abstract: A liquid crystal display device according to the present invention includes a liquid crystal panel having a vertical alignment type liquid crystal layer, and a drive circuit for supplying a driving voltage to the liquid crystal panel, and performs display in a normally black mode. At least at panel temperature 40° C., a rise transmittance Tr is equal to or greater than 75% of the transmittance in the highest gray scale level displaying state, and a decay transmittance Td is equal to or less than 8% of the transmittance in the highest gray scale level displaying state. At a panel temperature T1 below 40° C.
    Type: Application
    Filed: March 21, 2005
    Publication date: October 6, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masumi Kubo, Tomoo Furukawa
  • Publication number: 20050219445
    Abstract: The liquid crystal display device of the present invention includes a liquid crystal display panel 2 containing a liquid crystal having an alignment state which is so controlled that: a transmission intensity at an oblique viewing angle is greater than a frontal transmission intensity assuming a frontal transmittance of 1 for a white display and a transmittance of 1 at the oblique viewing angle for a white display; and a first region and a second region coexist in one or multiple picture element regions constituting a pixel, excess brightness occurring at the oblique viewing angle in the first region, no excess brightness occurring at the oblique viewing angle in the second region. The liquid crystal display device also includes a panel, 3, for use in viewing angle property control setting all or part of the second region of the liquid crystal display panel 2 to either a light-blocking state or a light-transmitting state as viewed from an oblique direction.
    Type: Application
    Filed: March 22, 2005
    Publication date: October 6, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Masumi Kubo
  • Publication number: 20050221214
    Abstract: Provided is a developing toner for electrostatic latent images capable of coping with the size reduction of an image forming apparatus and decrease of the consumption amount, not shortening the working life of a photoreceptor, less causing paper jam, background fogging, etc., excellent in various characteristics required for the toner, and capable of forming images of good picture quality. The developing toner being used when images are formed to a recording material in an image forming apparatus comprising an image forming station, a recording material feeding station, an image fixing station and a controlling station, the developing toner for electrostatic latent images containing hydrophobic fluidizing particles deposited to the surface of coloring resin particles comprising a binder resin containing a polyester resin, a polyalkylene, a polyolefin dispersant and a non-oxidized polyethylene resin, and an inorganic pigment, and having time constant ? of from 100 to 350 msec.
    Type: Application
    Filed: March 28, 2005
    Publication date: October 6, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hitoshi Nagahama, Tatsuo Imafuku, Takahiro Bito, Tenjiku Eiji, Takeshi Satoh, Ohkawa Takeshi
  • Publication number: 20050219182
    Abstract: The liquid crystal display device of the invention includes a plurality of pixels each having a first electrode, a second electrode facing the first electrode, and a vertically aligned liquid crystal layer placed between the first and second electrodes. The device further includes stripe-shaped first alignment regulating means having a first width placed in the first electrode side of the liquid crystal layer; stripe-shaped second alignment regulating means having a second width placed in the second electrode side of the liquid crystal layer; and a stripe-shaped liquid crystal region having a third width defined between the first and second regulating means. The third width is in a range between 7 ?m and 12 ?m.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 6, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hisakazu Nakamura, Masumi Kubo, Hiroyuki Ohgami, Tadashi Kawamura, Akihiro Yamamoto, Takashi Ochi, Yohichi Naruse
  • Publication number: 20050219453
    Abstract: The liquid crystal display device of the invention includes a plurality of pixels each having a first electrode, a second electrode facing the first electrode, and a vertically aligned liquid crystal layer placed between the first and second electrodes. The device further includes stripe-shaped first alignment regulating means having a first width placed in the first electrode side of the liquid crystal layer; stripe-shaped second alignment regulating means having a second width placed in the second electrode side of the liquid crystal layer; and a stripe-shaped liquid crystal region having a third width defined between the first and second regulating means. The third width is in a range between 2 ?m and 15 ?m.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 6, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masumi Kubo, Hisakazu Nakamura, Hiroyuki Ohgami, Akihiro Yamamoto, Tadashi Kawamura, Takashi Ochi, Yohichi Naruse
  • Publication number: 20050220499
    Abstract: A non-magnetic single component developing device that is included in combination with a photoreceptor in an image forming apparatus 1 of the electro-photographic system. The non-magnetic single component developing device includes a developing roller, a supplying roller, a doctor, a toner bath and a stirring blade. The supplying roller contains a rubber foam at least in its surface layer portion, the rubber foam including closed cells and open cells and having a foam ratio (porosity) of 0.75 to 0.85 and an average foam cell diameter of 350 to 500 ?m.
    Type: Application
    Filed: March 15, 2005
    Publication date: October 6, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Akihiko Kawahara, Tadayuki Sawai, Kazuya Korematu, Toru Nishikawa
  • Patent number: 6951802
    Abstract: A spin addition method for catalyst elements is simple and very important technique, because the minimum amount of a catalyst element necessary for crystallization can be easily added by controlling the catalyst element concentration within a catalyst element solution, but there is a problem in that uniformity in the amount of added catalyst element within a substrate is poor. The non-uniformity in the amount of added catalyst element within the substrate is thought to influence fluctuation in crystallinity of a crystalline semiconductor film that has undergone thermal crystallization, and exert a bad influence on the electrical characteristics of TFTs finally structured by the crystalline semiconductor film. The present invention solves this problem with the aforementioned conventional technique.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: October 4, 2005
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Misako Nakazawa, Toshiji Hamatani, Naoki Makita
  • Patent number: 6952192
    Abstract: A MVA type liquid crystal panel is slow in a response speed when a black state at a drive voltage about 1V is switched to a low brightness halftone state at the drive voltage about 2 to 3V. According to the present invention, in a liquid crystal display device for driving the MVA type liquid crystal panel, when a liquid crystal pixel at a pixel electrode is changed from a first transmittance to a second transmittance greater than the first transmittance, a drive voltage greater than a first target drive voltage in correspondence with a second transmittance is applied to the pixel electrode in a first frame period of changing to the second transmittance, and the first target display voltage is applied from a second frame period.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: October 4, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsufumi Ohmuro, Arihiro Takeda, Hideo Chida, Kimiaki Nakamura, Yoshio Koike
  • Patent number: 6952031
    Abstract: A nonvolatile semiconductor memory having a memory cell comprises: a semiconductor substrate having a pair of trenches formed on a surface thereof; first electrodes formed in a pair of trenches through the intervention of a first insulating film, respectively; a second electrode formed on the semiconductor substrate between the trenches through the intervention of a second insulating film; and a third electrode formed on the second electrode through the intervention of a third insulating film.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: October 4, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshimitsu Yamauchi
  • Patent number: 6952244
    Abstract: An active matrix devise comprises an array of picture elements. Each picture element has an image element, such as an LCD cell (11) connected to a first storage capacitor 12 and arranged to be connected to a data line 4 by an thin film transistor 10 when activated by a scan signal on a scan line 6. A second storage capacitor 21 can be connected across the first capacitor 12 by means of another thin film transistor 20 when desired so as to increase the storage capacitance at the pixel.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: October 4, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Graham Andrew Cairns, Catherine Rosinda Marie Armida Dachs, Michael James Brownlow, Yasuyoshi Kaise
  • Publication number: 20050213998
    Abstract: As outermost coating-like layer(s) of charging roller(s) is or are made to contact and/or slide against photosensitive drum(s), charge is applied from the outermost coating-like layer(s) to the photosensitive drum(s), charging the photosensitive drum(s). This being the case, resistance of the outermost coating-like layer(s) of the charging roller(s) fluctuates, and surface(s) thereof become scratched and so forth, and gradually deteriorate. Moreover, if remedial action is not taken, charging capability of the charging roller(s) may decrease, leading to nonuniformity in charging of the photosensitive drum(s) and causing lowering of image quality and/or reduction in service life of the photosensitive drum(s). The outermost coating-like layer(s) of the charging roller(s) is or are therefore periodically stripped off therefrom to rejuvenate the charging roller surface(s).
    Type: Application
    Filed: March 23, 2005
    Publication date: September 29, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kohji Shinkawa, Hiroshi Ishii
  • Publication number: 20050212023
    Abstract: A semiconductor memory device of the invention comprises a plurality of bit lines formed by implanting a second conductive-type impurity in a first conductive-type semiconductor substrate; a thick insulating film on the bit lines; a thin insulating film between the neighboring bit lines; and a plurality of word lines formed on the thick and thin insulating films so as to cross the bit lines, wherein each of the word lines includes a plurality of first conductors and a second conductor which electrically connects the first conductors in series, the respective first conductors are formed on the thin insulating film, the top face of the thickest portion of the thick insulating film is higher than the top face of the first conductors, and the film thickness of the thick insulating film is made thinner toward the end.
    Type: Application
    Filed: March 23, 2005
    Publication date: September 29, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Yoshimitsu Yamauchi
  • Patent number: D510230
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: October 4, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomoki Taira
  • Patent number: D510316
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 4, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Atsushi Hayakawa
  • Patent number: RE38806
    Abstract: A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: October 4, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuki Fukui, Yoshiki Sota, Yuji Matsune, Atsuya Narai