Abstract: A remote media player and methods for managing content. The media player includes a storage component to store content files. A user interface allows the user to make content selections. The content selections are used with a content database to manage the relationships between the selections and the content files. The player also includes a processor to perform organization tasks on the content files based upon the content selections.

Abstract: A method for current limiting of an output of a DC-to-DC converter begins by determining a current loading duty cycle of the output of the DC-to-DC converter (i.e., the present duty cycle given the loading of on the output). The processing then continues by comparing the current loading duty cycle with a zero loading duty cycle of the output (i.e., the duty cycle when the output has no load). The processing continues by limiting duty cycle of the output to the zero loading duty cycle plus a duty cycle loading offset when the current loading duty cycle exceeds the zero loading duty cycle plus the duty cycle loading offset.

Abstract: A remote media player and methods for managing content. The media player includes storage to store content files. A user interface allows the user to make content selections. The content selections are used with a content database to manage the relationships between the selections and the content files. The player also includes a processor to perform organization tasks on the content files based upon the content selections.

Abstract: A method for conserving power begins by measuring processing speed of at least a portion of an integrated circuit (IC) to produce measured processing speed. The portion of the IC may be a test circuit, a critical path of the IC, and/or a replica of the critical path of the IC. The processing continues by comparing the measured processing speed with a critical processing speed for the at least a portion of the integrated circuit. The processing then continues by adjusting supply voltage to the integrated circuit to reduce power consumption of the integrated circuit when the measured processing speed compares favorably to the critical processing speed.

Abstract: An amplifier circuit uses low threshold voltage devices for mid rail response in low voltage applications, but uses a high threshold voltage device at an output stage of the amplifier to generate an output from the amplifier.

Abstract: A method and apparatus for presenting content data and processing data includes processing that begins by receiving modulated display data and content data via a channel coupling an external content processing device to a content display device. The processing continues by separating the modulated data from the content data. The processing proceeds to retrieving display data from the modulated data and processing the display data for display. The processing continues by processing the content data for presentation.

Abstract: A configurable integrated circuit includes at least one general purpose input/output (GPIO) interface module, a first functional module, and a second functional module. The GPIO interface module includes a plurality of GPIO cells, wherein each of the GPIO cells is operably coupled to a corresponding pin of the configurable integrated circuit. When the configurable integrated circuit is in a first functional mode, at least one of the GPIO cells is operably coupled to its corresponding pin such that the corresponding pin functions as a digital input pin for the first functional module. When the configurable integrated circuit is in a second functional mode, at least one of the GPIO cells is operably coupled to its corresponding pin such that the corresponding pin functions as a digital output pin for the second functional module.

Abstract: A method and apparatus for regulating multiple outputs of a single inductor DC to DC converter includes processing that begins by producing a regulation signal to regulate a 1st output of the multiple outputs based on at least one of the multiple outputs. The processing then continues by identifying one of the multiple outputs to receive energy from the inductor during at least one cycle of the regulation signal. The processing continues by scaling the regulation signal for the at least one cycle based on the voltage of the particular output to receive the energy, the voltage of the 1st output and the supply voltage to the DC to DC converter when the particular output to receive the energy is not the 1st output. In this manner, when the output receiving the energy is not the 1st output (i.e., the directly regulated output), the regulation signal is scaled based on the desired duty cycle for the particular output.

Abstract: An overvoltage and backflow current protection circuit is employed when charging a battery. A switching circuit controls bias to the protection circuit to switch between overvoltage protection and backflow current protection.

Abstract: A variable bandgap reference includes a fixed bandgap reference source and a supply voltage dependent voltage divider module. The fixed bandgap produces a fixed reference voltage. The supply voltage dependent voltage adjust module adjusts the fixed reference voltage to produce the reference voltage.

Abstract: A computer audio system includes an audio codec and a tone controller. The audio codec is operably coupled to receive audio information, which includes tone control settings, PCM digital audio inputs and PCM digital audio outputs. In addition, the audio codec may receive audio information as analog input signals via a line-in, a CD input, or an auxiliary input. Based on the audio information, the audio codec provides a first stereo output, a second stereo output and a monotone audio output. The tone controller is operably coupled to the audio codec and includes a low pass filter, a high pass filter, a band pass filter, and a summing module. The low pass filter is operably coupled to filter the monotone audio output and isolates bass components of the audio signal being processed. By further coupling a volume control module to the low pass filter, the bass component of the audio signal being processed may be varied.

Abstract: An amplifier includes a transistor, a current source, a MOS capacitor, and a level shifting module. The transistor includes a gate, a drain, and a source, wherein the source of the transistor is operably coupled to a voltage node. The current source is operably coupled to provide a current to the drain of the transistor. The Metal Oxide Semiconductor (MOS) capacitor includes a gate, a drain, a source, and a well, wherein the drain, the well, and the source of the MOS capacitor are coupled together to form a first plate of the MOS capacitor and the gate of the MOS capacitor provides a second plate of the MOS capacitor, wherein the second plate of the MOS capacitor is operably coupled to the gate of the transistor, wherein the drain of the transistor provides an output for the amplifier and the gate of the transistor provides an input of the amplifier.

Abstract: A method and apparatus for recovering data by a digital audio interface, where the data may be transmitted over a single transmission path in accordance with the AES3-1992 standard, begins by receiving a stream of biphase encoded data. The biphase encoded data is organized as a series of data block that each include a plurality of frames. The processing continues by determining whether a next transition of a frame of the plurality of frames occurs during a first, second, or third time window after a preceding transition of the frame. When the next transition occurs during the second predetermined time, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the next transition and the preceding transition. In other words, the transitions of the data within the frame are occurring at the data rate.

Abstract: A method and apparatus for providing multiple channel audio in a computing system includes processing that begins by receiving an audio setup signal that indicates whether audio is to be outputted as stereo audio or multiple channel audio. When multiple channel audio is to be outputted, the line-in driver is disabled in the audio processing circuitry and the multiple channel driver of the audio processing circuitry is enabled. Thus, the multiple channel driver is operably coupled to the line-in audio jack. When the audio output is to be outputted as stereo audio, the multiple channel driver is disabled and the line-in driver is enable. Thus, the line-in driver is operably coupled to the line-in audio jack.

Abstract: A variable bandgap reference includes a fixed bandgap reference source and a supply voltage dependent voltage divider module. The fixed bandgap produces a fixed reference voltage. The supply voltage dependent voltage adjust module adjusts the fixed reference voltage to produce the reference voltage.

Abstract: A computer peripheral device includes circuitry that performs a computer peripheral function, a USB cable, and a USB\IR transceiver. The circuitry may be implemented to perform a mouse function, a keyboard function, a portable printer function, a microphone function, a hand scanner function, and/or a video camera function. The USB cable is operably coupled to provide connectivity with a computer to the circuitry and/or the USB/IR transceiver.

Abstract: A low loss multiple output stage of a boost converter includes a first output transistor having a first on-resistance, a second output transistor having a second on-resistance, a sink transistor, and a gate logic module. The sink transistor is operably coupled to allow energy to be provided to a first output via the first output transistor or to allow the energy to be provided to a second output via the gate logic module and the second output transistor based on a regulation signal. The gate logic module is operably coupled to, when the energy is to be provided to the first output, couple a gate and a well of the second output transistor to the first output; when the sink transistor is active, couple the gate and the well of the second output transistor to the second output, and when the energy is to be provided to the second output, couple the gate of the second transistor to ground and the well of the second output transistor to the second output.

Abstract: A method and apparatus that includes processing for recovering data that was transported utilizing multiple data transport protocols, where such processing begins by receiving formatted data and decoding the formatted data in accordance with a second data transport protocol. The decoding recaptures a first formatted data and a first data transport identifier. The processing then continues by decoding the first formatted data in accordance with a first data transport protocol based on the first data transport identifier. For example, if the first data transport protocol is one of the IrDA data transport protocols and the second data transport protocol is the USB data transport protocol, the decoding of the formatted data is to recapture the data that is formatted in accordance with the IrDA protocol, where the first transport identifier includes information that identifies the start of IrDA formatted data and its length. It turn, by decoding the IrDA formatted data, the original data is recaptured.

Abstract: A digital-to-analog converter includes a plurality of current sources, a differential amplifier, and a plurality of switching modules. The plurality of switching modules is operably coupled to the plurality of current sources and the digital amplifier module provides the analog output for the digital-to-analog converter. Each of the plurality of switching modules has a corresponding current source of the plurality of current sources, where a 1st set of the plurality of switching modules couples the corresponding current sources to the differential amplifier module in a 1st manner based on a digital input value and a 2nd set of the plurality of switching modules couples the corresponding current sources to the differential amplifier in a 2nd manner based on the digital input values such that, over time, errors introduced by the coupling in the 1st manner substantially compensates for errors introduced by the coupling in the 2nd manner.

Abstract: An edge sensitive detection circuit includes a filter module and a soft latch module. The filter module is operably coupled to receive an input logic signal that corresponds to the triggering of an event and produces a pulse signal in response to an edge of the input logic signal. The filter may include a capacitor operably coupled to a controlled impedance, an inverter and a driver transistor, wherein the capacitor senses an edge of the input logic signal and, in combination with the controlled impedance, produces the pulse signal. The soft latch module is operably coupled to receive the pulse signal and to latch a logic value in accordance with the pulse signal.