Abstract: A phase locked loop circuit is implemented with difference detection module that produces a difference signal based on at least one of phase difference and frequency difference between a reference oscillation and a feedback oscillation. A loop filter module converts the difference signal into a control signal. A controlled oscillation module converts the control signal into an output oscillation. An output oscillation adjust module, coupled to the controlled oscillation module, produces an effective output oscillation based on an oscillation control signal. A divider module converts the effective output oscillation into the divided oscillation. A delay adjust module provides an adjustable delay to produce the feedback oscillation.

Abstract: The disclosure is directed to a method of determining memory parameters of a memory device. The method includes determining a communication protocol associated with the memory device, determining a page size of the memory device by using the communication protocol to communicate a page of data, determining a block size of the memory device by using the communication protocol to erase a block of the memory device, and determining a capacity of the memory device by using the communication protocol to determine a number of significant address bits.

Abstract: A system and method for decoding a received television signal is disclosed. The system includes an input to receive a digital audio signal and a digital variable deemphasis module to modify the amplitude of the digital audio signal based on a plurality of variable coefficients. The system also includes an exponential digital root mean square (ERMS) detector to provide level detection of the digital audio signal. The plurality of variable coefficients of the digital variable deemphasis module are digitally computed based on an output of the digital ERMS detector.

Abstract: The disclosure is directed to a method of managing data storage. The method includes detecting an unusable memory block. The unusable memory block is in a set of user accessible memory blocks of a memory device. The memory device includes the set of user accessible memory blocks, a set of defective memory blocks, and a set of replacement memory blocks. The set of user accessible memory blocks includes not more than one half of a total number of memory blocks of the memory device and includes memory blocks from both halves of the memory device as addressed by a significant address bit. The method also includes indicating that the unusable memory block is a defective memory block and includes allocating a replacement memory block from the set of replacement memory blocks to the set of user accessible memory blocks.

Abstract: A programmable sample rate ADC includes a delta sigma modulator for producing a digital signal, and a programmable decimation filter, that includes X stages of integration, a down-sampling stage for down-sampling by a factor of N, and Y stages of differentiation. The programmable sample rate ADC produces a digital output signal at a substantially constant frequency.

Abstract: A system and method of providing a voltage to a non-volatile memory is disclosed. The system includes an output pin to provide an output voltage to a non-volatile memory and includes a memory to store a table. The table includes a plurality of operating voltage levels. The system further includes a voltage mode module to apply a first voltage at a first of the plurality of operating voltage levels at the output pin prior to a read operation on the non-volatile memory. The voltage mode module applies a second voltage at a second of the plurality of voltage levels at the output pin in response to a read operation that returns a failure condition.

Abstract: A method for use in a multifunction handheld device includes receiving a first plurality of digitally formatted files from a host device when coupled to the host device via a host interface. A selected one of the first plurality of digitally formatted files is played, the playing includes generating an audio output. The method monitors for a low voltage condition produced by a low battery voltage. When the low voltage condition is detected, a first fail safe algorithm is enabled to disable the audio output, store an audio setting corresponding to the playing of the audio output, and to shutdown the multifunction handheld device.

Abstract: A delay lock loop for use in meeting SDRAM timing requirements, wherein a timing relationship between data generated by a computer chip and a clock in said DRAM is fully programmable, and wherein said delay lock loop is digitally implemented. The delay lock loop includes a first delay chain to measure a number of delay taps in a single clock cycle of the clock of the SDRAM and a second delay chain to delay the clock of the SDRAM. The second delay chain is matched to the first delay chain.

Abstract: An analog-to-digital converter (ADC) system is disclosed and includes a programmable control register and a plurality of channels, each channel having an associated request bit within the programmable control register. The ADC system also includes a scheduler responsive to the programmable control register, the scheduler comprising logic to monitor a plurality of request bits to detect when any of the request bits are set. A method of scheduling analog-to-digital conversion is disclosed and includes receiving a request to schedule an analog-to-digital conversion for a channel of a plurality of channels. The method also includes scheduling an analog-to-digital conversion in response to receiving the request and performing the analog-to-digital conversion based on the request, where data that indicates the request is stored in a programmable control register.

Abstract: Disclosed is a digital audio device that includes a communications port to communicatively connect the device to a server. The device also includes a unique identifier to identify the device. The device also includes a controller to allow transfer of digital audio files from the server. The digital audio files contain interleaved data selected by the server based on the unique identifier. The device also includes a decoder to decode the interleaved data and a data store to store at least one of the digital audio files and the interleaved data.

Abstract: A RGB to YUV conversion is presented that provides separate lumina and chroma filtering to produce the Y data block, and the U and V data blocks. Lumina filter interpolation is performed with, for example, a 5-tap filter while chroma filtering interpolation is performed with, for example, a 7-tap filter. The filtering arrangements take advantage of the eye's higher visual sensitivity to spatial variation compared to color variation.

Abstract: A method and system for sensing the temperature of an integrated circuit are presented. The method compares a first current that is proportional to a temperature reading of the integrated circuit to a reference current. While the first current is greater than the reference current, a counter is incremented, and the reference current is increased in response to incrementing the counter. A system for sensing the temperature of an integrated circuit includes a first current source providing a source current to a node. The first current source is based on an input from a proportional to absolute temperature device. The system also includes a second current source providing a sink current to the node, with the amount of sink current being based on an input from a digital control module. The system also includes a comparator coupled to the node to provide a comparator signal that indicates a relationship between the source current and the sink current.

Abstract: An ESD protection circuit for an integrated circuit includes an ESD clamping circuit, an ESD triggering circuit, and an ESD disabling circuit. The ESD clamping circuit is operably coupled to a first power pin of the integrated circuit and a second power pin of the integrated circuit. The ESD triggering circuit is operably coupled to the ESD clamping circuit, wherein, when enabled and when sensing an ESD event, the ESD triggering circuit provides a clamping signal to the ESD clamping circuit such that the ESD clamping circuit provides a low impedance path between the first and second power pins. The ESD disabling circuit is operably coupled to disable the ESD triggering circuit when the integrated circuit is in a normal operating mode.

Abstract: A current threshold circuit includes a series impedance, a reference voltage source, and a comparison module. The series impedance couples an output of a current source to a load, wherein impedance of the series impedance is substantially less than impedance of the load. The reference voltage source is operably coupled to produce a reference voltage differential. The comparison module is operably coupled to compare the reference voltage differential with a differential voltage of the series impedance, wherein the comparison module generates an excessive current indication when the differential voltage of the series impedance compares unfavorably to the reference voltage differential.

Abstract: The disclosure is directed to a device including a memory interface. The memory interface includes a data interface, a first state machine and a second state machine. The first state machine includes a first chip select interface and a first ready/busy interface. The first state machine is configured to select and monitor a first memory device via the first chip select interface and the first ready/busy interface, respectively, when the first memory device is coupled to the data interface. The second state machine includes a second chip select interface and a second ready/busy inter-face. The second state machine is configured to select and monitor a second memory device via the second chip select interface and the second ready/busy interface, respectively, when the second memory device is coupled to the data interface.

Abstract: A semiconductor device includes a plurality of laser fuses and each laser fuse represents a bit of data. A first set of the plurality of laser fuses represents a unique identifier that corresponds to the semiconductor device. Also, a second set of the plurality of laser fuses represents error correction coding data that corresponds to the unique identifier. The unique identifier can be a digital rights management identification. Also, the error correction coding data is configured for use by a Reed-Solomon error correcting method to correct the unique identifier. Alternatively, the error correction coding data is configured for use by a cyclic redundancy check method.

Abstract: A system is disclosed that comprises a processor, a memoryless first level page table addressable by the processor, and a second level page table stored in a memory coupled to the processor. The second level page table is addressable by at least one entry of the first level page table.

Abstract: A system and method to provide voltage to a device from the operating mode of an integrated circuit is disclosed. In a particular embodiment, the disclosed system includes an integrated circuit having an input/output pin and a DC-DC converter circuit that is coupled to the input/output pin and including a transistor element. The DC-DC converter circuit has a first mode of operation and a second mode of operation. In the first mode of operation, the DC-DC converter circuit performs voltage conversion and in the second mode of operation, the transistor element of the DC-DC converter circuit is used to selectively apply a voltage supply to an external module coupled to the input/output pin.

Abstract: The disclosure includes a system and method of using a processor and protected memory. In a particular embodiment, the system includes a processor, a volatile memory accessible to the processor, and a first nonvolatile memory accessible to the processor. The first nonvolatile memory includes a first portion of memory that is protected and is readable when a shield bit indicates an unshielded mode of operation, but is unreadable when the shield bit indicates a shielded mode of operation and a second portion of memory that is unprotected and that is readable regardless of the value of the shield bit. The system includes a second nonvolatile memory including data to be transferred to the volatile memory.

Abstract: A digital audio device including a communications port to connect the device to a server and a controller to allow transfer of digital audio files from the server. The digital audio files may include non-audio data interleaved with the digital audio files and the device will include a decoder to decode the non-audio data.