Patents Assigned to SigmaTel, Inc.
  • Patent number: 6654900
    Abstract: A method and apparatus for producing multiple clock signals having controlled duty cycles and phase relationships includes processing that begins by generating a plurality of delayed clock signals from an input clock signal based on a delay control signal. The processing then continues by producing a first multiple clock signal from a first set of a plurality of delayed clock signals and the input clock signal. The processing then continues by producing a second multiplied clock signal from a second set of the plurality of delayed clock signals, where the second multiplied clock signal is delayed from the first multiplied clock signal in accordance with a delay of at least one of the delayed clock signals. The processing then continues by generating the delayed control signal based on the first multiplied clock signal, where the delay control signal controls delays of the plurality of delayed clock signals.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: November 25, 2003
    Assignee: Sigmatel, Inc.
    Inventor: Michael D Cave
  • Patent number: 6633187
    Abstract: A method and apparatus for enabling a stand-alone integrated circuit (IC) includes processing that begins by establishing an idle state that holds at least a portion of the stand-alone integrated circuit in a reset condition when a power source is operably coupled to the stand-alone integrated circuit. A stand-alone integrated circuit includes generally an on-chip power converter, a reset circuit and some functional circuitry, which may be a microprocessor, digital signal processor digital circuitry, state machine, logic circuitry, analog circuitry, and/or any type of components and/or circuits that perform a desired electrical function. When a power enable signal is received, the on-chip power converter is enabled to generate at least 1 supply from the power source. The processing continues by enabling functionality of the stand-alone integrated circuit when the at least one supply has substantially reached a steady state condition.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: October 14, 2003
    Assignee: Sigmatel, Inc.
    Inventors: Michael R. May, Marcus W. May
  • Patent number: 6608902
    Abstract: A stereo separation circuit includes a pair of amplifiers and a pair of divider circuits. Each of the amplifiers is coupled to receive a stereo signal (e.g., a left stereo signal or a right stereo signal) and the output of the other amplifier through a portion of one of the divider circuits. The other portion of the divider circuit is coupled as feedback across an amplifier. A ratio between the feedback portion of the divider circuit and the other portion of the divider circuit provides a separation ratio. The greater the separation ratio, the greater the perceived audio separation of the stereo signals.
    Type: Grant
    Filed: February 7, 1998
    Date of Patent: August 19, 2003
    Assignee: Sigmatel, Inc.
    Inventors: H. Spence Jackson, Mathew A. Rybicki, Giri Nk Rangan
  • Patent number: 6584162
    Abstract: A method and apparatus for sample rate conversion in an analog to digital converter. Such a method and apparatus include processing that begins by receiving an input digital stream at a first clock rate from an oversampling quantizer (e.g., a sigma delta modulator). The processing continues by integrating the input digital stream over multiple clock cycles at the first clock rate to produce an integrated digital signal. The processing continues by determining when an interpolated digital value of the integrated digital signal is to be passed to a differentiation stage based on a difference between a sample rate conversion value and a reference value. The processing continues by, when the difference is within a targeted range (e.g.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: June 24, 2003
    Assignee: Sigmatel, Inc.
    Inventor: Darrell E. Tinker
  • Patent number: 6567027
    Abstract: A method and apparatus for analog to digital conversion includes processing that begins by quantizing an analog input signal to produce a stream of digital data at an over sampling rate. The processing continues by producing partially filtered data based on a moving sum of the stream of data. The processing continues by decimation filtering the partially filtered data to produce a digital output value.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: May 20, 2003
    Assignee: Sigmatel, Inc.
    Inventor: Michael R. May
  • Patent number: 6535901
    Abstract: A method and apparatus for generating a fast multiply accumulation circuit includes processing that begins by determining number of current partial products for a multiplication of a first multiplicand and a second multiplicand. The processing then continues by determining size of the current partial products. The processing then continues by identifying one of a plurality of reduction patterns based on the size of the current partial products. The processing then continues by determining number of, and configuration of, full adders and half adders required for a reduction function of the current partial products based on the one of the plurality of reduction patterns and the size of the current partial products, wherein the multiply-accumulator performs the reduction function.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: March 18, 2003
    Assignee: Sigmatel, Inc.
    Inventor: Robert T Grisamore
  • Patent number: 6526111
    Abstract: A phase lock loop includes a phase detector, a charge pump circuit, a controlled oscillator, and a jitter control circuit. The control oscillator may also include a biasing circuit to provide the frequency biasing. The phase detection circuit is operably coupled to receive the reference signal and a feedback signal and to produce therefrom a phase different signal. The phase different signal is provided to the charge pump circuit, which includes a first current source and a second current source. The first current source is dominate when the phase different signal is in a first stage (e.g., charge up) and the second current source is dominate when the phase signal is in the second state (e.g., charge down). The charge pump circuit outputs a representative signal that is provided to the control oscillator which, in response, generates the output signal. The output signal is fed back to the phase detection circuit as the feedback signal.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: February 25, 2003
    Assignee: Sigmatel, Inc.
    Inventor: Ammisetti V Prasad
  • Patent number: 6522511
    Abstract: An electrostatic discharge (ESD) protection circuit for use in an integrated circuit includes a transistor, an inverter, and an ESD detector. The transistor is coupled to clamp a non-power supply pad of the integrated circuit to a power supply pad of the integrated circuit when an ESD event is detected. The ESD detector is operably coupled to detect an ESD event on the non-power supply pad and to provide an indication of the ESD event to the inverter. The inverter provides an amplified signal to the gate of the transistor such that the transistor is driven quickly into low impedance conduction.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: February 18, 2003
    Assignee: Sigmatel, Inc.
    Inventors: Willis John, May Mike, Takeda Fujio
  • Patent number: 6522275
    Abstract: A method and apparatus for sample rate conversion in an analog to digital converter includes processing that begins by converting an analog input signal into a stream of digital data. The processing continues by determining an up sampling value and a down sampling value based on a sample rate conversion value. The processing continues by computing a moving sum of data of the stream of data based on the up sampling value, the clock rate of the stream of data, and a predetermined filter function. The processing continues by producing a digital output value from the moving sum based on the down sampling value, wherein the digital output value is at a desired output rate.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: February 18, 2003
    Assignee: Sigmatel, Inc.
    Inventor: Michael R. May
  • Patent number: 6507223
    Abstract: A differential line driver that includes a 1st operational amplifier, a 2nd operational amplifier, an adjustable reference module, a 1st feedback impedance, and a 2nd feedback impedance. First inputs (e.g. the inverting input or non-inverting input) of the 1st and 2nd operational amplifiers are coupled to receive an input signal. The 2nd inputs (e.g. the compliment of the 1st input) of the 1st and 2nd operational amplifiers are operably coupled to receive an adjustable reference voltage from the adjustable reference module. The adjustable reference module provides the adjustable reference voltage based on the common mode of the power source for the 1st and 2nd operational amplifiers (e.g. Vdd, Vss) and/or the common mode of the input signal. The 1st and 2nd feedback impedances, (e.g. resistors) are coupled from the output of the respective operational amplifiers to either the 1st or 2nd input of the respective operational amplifiers.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: January 14, 2003
    Assignee: Sigmatel, Inc.
    Inventor: Matthew D. Felder
  • Publication number: 20020145547
    Abstract: A method and apparatus for analog to digital conversion includes processing that begins by quantizing an analog input signal to produce a stream of digital data at an over sampling rate. The processing continues by producing partially filtered data based on a moving sum of the stream of data. The processing continues by decimation filtering the partially filtered data to produce a digital output value.
    Type: Application
    Filed: February 8, 2001
    Publication date: October 10, 2002
    Applicant: SigmaTel, Inc.
    Inventor: Michael R. May
  • Publication number: 20020110187
    Abstract: A method and apparatus for domain conversions for multiple channels within a single analog front-end include processing that begins by generating a system clock. The processing continues by converting a frequency of 1st data from a 1st channel frequency to a 2nd channel frequency based on a 1st integer ratio of the system clock. The processing continues by converting the domain of the 1st data rate from a 1st domain to a 2nd domain. The processing continues by converting a frequency of the 2nd data of a 2nd channel from a 2 channel frequency to the 2nd frequency based on a 2nd integer ratio of the system clock. For example, the rate of the 2nd data may be different than the rate of the 1st but both are converted to the 2nd frequency, which is universally used within the analog front-end. The proceeding continues by converting the domain of the 2nd data from the 1st domain to the 2nd domain.
    Type: Application
    Filed: February 13, 2001
    Publication date: August 15, 2002
    Applicant: SigmaTel, Inc.
    Inventor: Michael R. May
  • Publication number: 20020110210
    Abstract: A method and apparatus for adjusting timing in a digital system or telecommunication system includes processing that begins by dividing a data clock by a 1st value to produce a divided data clock. The processing continues by dividing an analog front-end clock by a 2nd value to produce a divided analog front-end clock. The 1st and 2nd values are selected such that the divided data clock and the divided analog front-end clock have similar clock rates. The processing continues by comparing the phase of the divided data clock with the phase of the divided analog front-end clock to produce a phase difference. The processing continues by adjusting the analog front-end clock based on the phase difference to produce an adjusted analog front-end clock.
    Type: Application
    Filed: February 13, 2001
    Publication date: August 15, 2002
    Applicant: SigmaTel, Inc.
    Inventors: Michael R. May, Carlin D. Cabler
  • Publication number: 20020099966
    Abstract: A method and apparatus for waking up a circuit includes processing that begins by determining whether a signal is present on a data path by a 1st detection module. The 1st detection module is designed with passive components such that it consumes a minimal amount of power. In addition, the 1st detection module detects the presence of any signal on the received path using the energy of the signal. When a signal is detected, a 2nd detection module is enabled to determine whether a characteristic of the signal is one of a known set of characteristics. The known set of characteristics includes a phase relationship, magnitude, power level, frequency, and/or any other characteristic a telecommunication system may have. When the characteristic of the signal is one of the known set of characteristics, the digital circuitry of a modem is enabled.
    Type: Application
    Filed: January 25, 2001
    Publication date: July 25, 2002
    Applicant: SigmaTel, Inc.
    Inventor: Carlin D. Cabler
  • Patent number: 6404172
    Abstract: A method and apparatus for integrating buck or boost converting includes processing for controlling the configuration of transistors, an inductor, a power source, and a load to provide buck or boost converting. Such processing begins by determining whether a buck/boost signal is indicating buck operation or boost operation. If the buck/boost signal is indicating buck operation, the processing proceeds by generating a buck control signal and a load control signal. The buck control signal is provided to the transistors such that the transistors are coupled to a power source and the inductor to provide a buck converter. The load control signal is provided to a load transistor to regulate the output with respect to the load. When the bucklboost signal indicates boost operation, the processing generates a boost control signal and a load control signal. The boost control signal is provided to the transistors such that the transistors are coupled to the power source and the inductor to provide a boost converter.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: June 11, 2002
    Assignee: Sigmatel, Inc.
    Inventor: Marcus W. May
  • Publication number: 20020063650
    Abstract: An improved switch capacitor circuit includes a capacitor, a 1st voltage reference module, a 2nd voltage reference module, and a plurality of switching elements. The capacitor is operably coupled via the plurality of switching elements to sample an input signal during a 1st interval of a sampling period and during a 2nd interval of the sampling period to provide a representation of the input signal. The 2nd reference module produces a 2nd reference voltage that is representative of the common mode of the supply (e.g. VDD and VSS). The 1st voltage reference module produces a 1st reference voltage that is representative of the common mode of the analog input signal. As such, the capacitor is charged during the 1st interval based on the 1st reference voltage and discharged during the 2nd interval based on the 2nd reference voltage.
    Type: Application
    Filed: November 30, 2000
    Publication date: May 30, 2002
    Applicant: SigmaTel, Inc.
    Inventor: Willis John
  • Patent number: 6373277
    Abstract: A line driver having variable impedance termination includes an impedance, a 1st variable feedback, a 2nd variable feedback, a summing module and a gain module. The 1st and 2nd variable feedbacks provide feedback based on the desired impedance for the particular application. The summing module is operably coupled to sum the 1st variable feedback, the 2nd variable feedback and a signal to produce a resultant signal. The gain module is operably coupled to receive the resultant signal and to amplify the signal to produce a gained signal. The output of the gain module is operably coupled to the impedance wherein the other node of the impedance provides the output of the line driver. To provide the feedback, the 1st variable feedback is operably coupled to the output of the gain module and the summing module and the 2nd variable feedback is operably coupled to the output of the line driver and the summing module.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: April 16, 2002
    Assignee: Sigmatel, INC
    Inventor: Matthew D. Felder
  • Patent number: 6366522
    Abstract: A method and apparatus for controlling power consumption of an integrated circuit include processing that begins by producing a system clock from a reference clock based on a system clock control signal. The reference clock may be generated from an external crystal oscillator circuit operable to produce a reference clock at a desired frequency. The processing continues by regulating at least one supply from a power source and an inductor based on a power supply control signal. The processing continues by producing the system clock control signal and the power supply control signal based on a processing transfer characteristic of a computational engine and processing requirements associated with processing at least a portion of an application by the computational engine.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: April 2, 2002
    Assignee: Sigmatel, Inc
    Inventors: Marcus W. May, Daniel Mulligan
  • Patent number: 6362755
    Abstract: A method and apparatus for converting sample rates of digital signals includes processing that begins by receiving an input data stream at a first sample rate. The processing continues by retrieving predetermined integrated samples at the first sampling rate, where the predetermined integrated samples are derived based on a ratio between the first sampling rate and a second sampling rate. The processing then continues by adjusting the retrieved predetermined integrated samples based on data values of the input data stream to produce adjusted integrated samples. The processing continues by differentiating the adjusted integrated samples to produce an output data stream at an output sample rate, wherein the second sample rate is a multiple of the output sample rate.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: March 26, 2002
    Assignee: Sigmatel, Inc.
    Inventor: Darrell E Tinker
  • Patent number: 6362605
    Abstract: A method and apparatus for efficiently powering an integrated circuit include processing that begins by generating a representation of a battery voltage. The processing then continues by producing a regulated bias current based on the representation of the battery voltage. The processing continues by providing the regulated bias current to an external crystal, which, in turn, generates an oscillation in response to the bias current. The processing then continues by generating a clock signal from the oscillation produced by the external crystal. The clock signal is then provided to a DC-to-DC converter that converts the battery voltage into a regulated output voltage.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: March 26, 2002
    Assignee: Sigmatel, Inc.
    Inventor: Michael R May