Abstract: A switching amplifier system and method is disclosed. In a particular embodiment, a pulse width modulation frame size is determined based on a sample rate of a digital input signal. Data associated with the first digital input signal is modified based on the pulse width modulation frame size. A pulse width modulation signal is generated in response to the modified data.

Abstract: A demodulator system and method is disclosed. In an embodiment, the demodulator system can include a Coordinate Rotation Digital Computer (CORDIC) mixer to mix a first signal substantially to baseband using a first input frequency and to mix a second signal substantially to baseband using a second input frequency. In another embodiment, the demodulator system can include a phase detector to receive a pilot signal and to generate a control signal to adjust a decimation rate based on the pilot signal. In another embodiment, the demodulator system can include a symbol decoder to determine a symbol from a phase signal.

Abstract: A digital audio processing system and method is disclosed. In an embodiment, the digital audio processing system can include a phase detector to sample an input signal and provide an output to adjust a decimation rate of an input signal. In another embodiment, the digital audio processing system can include symbol recognition logic to determine a symbol using a difference between a nearest predetermined phase value to a sample and a nearest predetermined phase value to a prior sample.

Abstract: A digital mixer system and method is disclosed. In an embodiment, a digital mixer can receive a modulated signal having a sample rate approximately equal to a clock rate divided by an integer factor. The digital mixer can include a first mixing stage having a first plurality of Coordinate Rotation Digital Computer (CORDIC) elements to serially perform a predetermined number of consecutive CORDIC iterations per clock cycle. The first mixing stage can further have logic to selectively process data received from an output of the first mixing stage. The digital mixer can also include a second mixing stage having a second plurality of CORDIC elements to serially perform a number of consecutive CORDIC iterations per clock cycle. The second mixing stage can also have logic to selectively process data received from an output of the first mixing stage and from an output of the second mixing stage.

Abstract: An overvoltage and backflow current protection circuit is employed when charging a battery. A switching circuit controls bias to the protection circuit to switch between overvoltage protection and backflow current protection.

Abstract: A system and method to provide voltage to a device from the operating mode of an integrated circuit is disclosed. In a particular embodiment, the disclosed system includes an integrated circuit having an input/output pin and a DC-DC converter circuit that is coupled to the input/output pin and including a transistor element. The DC-DC converter circuit has a first mode of operation and a second mode of operation. In the first mode of operation, the DC-DC converter circuit performs voltage conversion and in the second mode of operation, the transistor element of the DC-DC converter circuit is used to selectively apply a voltage supply to an external module coupled to the input/output pin.

Abstract: A memory includes at least one memory segment that includes an array of memory cells arranged in a plurality of columns, each of the plurality of columns having a corresponding bitline pair. An address decoder includes a row decoder and a column decoder that addresses a selected one of the array of memory cells in a selected one of the plurality of columns in response to a memory address. A sense amplifier generates a data output by sensing a differential voltage from the corresponding bitline pair of the selected one of the plurality of columns in response to a sense amp enable signal. A sense amp enable signal generator generates the sense amp enable signal with adjustable timing, based on sense amp feedback signals.

Abstract: A system and method for providing direct memory access is disclosed. In a particular embodiment, a direct memory access module is disclosed that includes a memory, a first interface coupled to a processor, and a second interface coupled to a peripheral module. A first instruction received from the first interface is stored in the memory. The first instruction includes a number of programmed input/output words to be provided to the peripheral module via the second interface. The direct memory access module also includes an instruction execution unit to process the first instruction.

Abstract: A microphone bias circuit includes a first integrated circuit (IC) pin, a second IC pin, a first resistor, and a variable supply voltage buffer. The first resistor is operably coupled to the first IC pin and a return voltage. The second IC pin is operably coupled to receive analog signals from a microphone. The variable supply voltage buffer is operably coupled to produce a buffered supply voltage based on a variable impedance setting, wherein at least one off-chip component couples the second IC pin to the first IC pin and wherein the variable supply voltage buffer provides the buffered supply voltage to second IC pin as a microphone bias voltage.

Abstract: The programmable analog input/output integrated circuit system includes a plurality of integrated circuit pins, an analog input/output circuit, a control module, and a switching module. The analog input/output circuit is coupled to the plurality of pins and determines the input/output status of each of the pins. The control module generates an I/O control signal and a switching control signal based on the input/output status of the integrated circuit pins. The I/O control signal is provided to the analog I/O circuit, which configures itself as an input or output based on the I/O control signal. The control module provides the switching control signal to the switching module, which configures itself to couple the analog input and/or analog output to corresponding functional circuitry of the corresponding integrated circuit.

Abstract: An implementation of an MPEG-4 compliant post-filter for image data, which performs deblocking and deringing post-filtering on decoded video data. The post-filter comprises two independent processing units, one for horizontal deblocking and the other for vertical deblocking and deringing, each processing unit in communication with a memory system, which can include DRAM. The post-filter further comprises a local memory, which can be SRAM, for high speed access to data being processed by the vertical deblocking and deringing filter, without additional accesses to the memory system. Further, horizontal deblocking and vertical deblocking and deringing functions can be performed concurrently in a pipe-lined fashion.

Abstract: A differential audio amplifier includes a differential input stage for producing an output voltage in response to a differential audio input signal. The differential input stage has a first bias voltage and a second basis voltage. A bias compensation module controls the first bias voltage to be substantially equal to the second bias voltage.

Abstract: A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read current generator controls the source current to the memory cell to a read current state when a column containing the memory cell is selected.

Abstract: A system and method of synchronizing to a frame sequence in an input signal includes tolerating data errors within certain error thresholds. In an embodiment, a Hamming distance between data included in a frame alignment word field and an expected value is compared to a predetermined Hamming distance to determine a synchronization event.

Abstract: A system on a chip integrated circuit includes a first circuit module and N other circuit modules that are operable to produce at least one output signal based on at least one input signal. A reference oscillator for generating a base clock signal for the first circuit module. A clock delay generator generates N delayed clock signals at a corresponding N clock delays, wherein N is greater than or equal to 2. The N delayed clock signals are provided to the N other circuit modules.

Abstract: An amplifying circuit includes an input chopping circuit, an amplifier, and an output chopping circuit. The input chopping circuit is operably coupled to chop an input signal at a chopping rate to produce a chopped input signal. The amplifier has a first input transistor section, a second input transistor section, and a transistor load section. The first and second input transistor sections are operably coupled to receive the chopped input signal, wherein the first input transistor section amplifies the chopped input signal when the chopped input signal is in first signal level range, the second input transistor section amplifies the chopped input signal when the chopped input signal is in a second signal level range, and the first and second input transistor sections amplify the chopped input signal when the chopped input signal is in a third signal level range, wherein the transistor load section is coupled to the first and second input transistors sections to produce an amplified chopped signal.

Abstract: A method and apparatus for regulating multiple outputs of a single inductor DC to DC converter includes processing that begins by producing a regulation signal to regulate a 1st output of the multiple outputs based on at least one of the multiple outputs. The processing then continues by identifying one of the multiple outputs to receive energy from the inductor during at least one cycle of the regulation signal. The processing continues by scaling the regulation signal for the at least one cycle based on the voltage of the particular output to receive the energy, the voltage of the 1st output and the supply voltage to the DC to DC converter when the particular output to receive the energy is not the 1st output. In this manner, when the output receiving the energy is not the 1st output (i.e., the directly regulated output), the regulation signal is scaled based on the desired duty cycle for the particular output.

Abstract: A printing system comprising a set of nozzles for applying a color component, wherein each of the nozzles in the set is configured to apply a different effective color intensity; and a raster associated with the set of nozzles, the raster comprising a plurality of cells wherein each cell in the plurality of cells comprises at least one element which represents the effective color intensity to be applied to an area by the set of nozzles, wherein the number of elements in a cell is less than the range of different effective color intensities.

Abstract: A system includes a first semiconductor device, a second semiconductor device, and an external crystal oscillator. The first semiconductor device includes a source voltage output and an external pin input. The first semiconductor device includes a direct current-to-direct current (DC-DC) converter circuit that provides the source voltage output. The second semiconductor device includes a source voltage input that is coupled to the source voltage output of the first semiconductor device and includes a clock signal output. The external crystal oscillator is coupled via an input of the second semiconductor device to a first oscillator clock generation circuit.

Abstract: A memory includes a selected bitline coupled to the array of memory cells. A column voltage booster produces a boosted column enable signal. A column multiplexer passes a signal on the selected bitline as a sense amplifier input in response to the boosted column enable signal. A sense amplifier produces a data output.