Abstract: An apparatus and a process for transferring packet data includes receiving packets from a first interface such as a network interface and transferring data to a second interface such as an SD Bus interface such as SDIO using a protocol such as one described in SDCard.org. The SD Bus second interface operates as a slave device to a master device, and the packet transfer from first interface to second interface includes concatenating length fields and packet data fields from packets received on the first interface to form a superframe which is provided to the second interface at time of data transfer. The formation of each superframe includes starting a timer such that the superframe is transmitted to the second interface by asserting an interrupt on that interface when either the timer expires, the number of packet from the first interface exceeds a threshold, or the amount of data from the first interface exceeds a threshold.

Abstract: A process for equalizing streams of OFDM subcarrier data computes the noise variance for each stream, and forms a stream weighting coefficient by equalizing the noise variance, such that for a first stream having a noise variance ?1 and a second stream having a noise variance of ?2, the first stream is scaled by k 1 = 2 ? ? 2 ? 1 2 + ? 2 2 and the second stream is scaled by k 2 = 2 ? ? 1 ? 1 2 - ? 2 2 .

Abstract: A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.

Abstract: A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of the first delay coupled to a second delay generating an output. The first and second delay are substantially equal to a preamble part. A first multiplier generates an output from a conjugated output of the second delay output and a first delay output. A second multiplier generates an output from a conjugated first delay output and an input stream. The first and second multiplier outputs are accumulated over an interval, and the complex output of the accumulator is formed into a magnitude, thereby generating the output of each preamble processor. The outputs of the preamble processors are summed and compared to a threshold to generate a preamble detect.

Abstract: A computer-implemented method and system are provided for assisting a plurality of patients manage chronic health conditions.

Abstract: An OFDM symbol comprises information subcarriers which carry the information to be transmitted, accompanied by edge subcarriers, which are selected to minimize the PAPR of the transmitted signal. The selection of edge subcarriers which minimizes PAPR enables either higher power transmission for the same information content, or lower power consumption for the same transmitted symbol power.

Abstract: A reduced complexity maximum likelihood decoder receives a stream of symbols Y and channel estimate H. A transformation converts Y and H into Z and R by computing matrix R, such that the product of R and Q produces matrix H. A second transformation column-swaps matrix H to form H?, thereafter generating Q? and R? subject to the same constraints as was described for Q and R. Transformed variables Z and Z? are formed by multiplying Y by QH and Q?H, respectively. Table entries with Z and R and Z? and R? have entries of all possible x2 accompanied by estimates of x1 derived from x2 and Z, and similar entries of all possible x1 accompanied by estimates of x2 derived from x1 and Z?. Hard and soft decisions are made by finding the minimum distance metric of the combined entries of the first and second table.

Abstract: A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with said pointers to be applied to a media access controller, which optionally contains an encryption function, the output of which is coupled to a block buffer and to an output interface. Upon receipt of a transmission request, the host memory locations associated with the pointers are read and the data directed to the media access controller, which adds a header, a CRC, and optionally encrypts the data, thereafter placing it in the block buffer and the output interface. Upon provision of the packet data to the MAC, the associated pointer is initialized to a FREE or UNUSED value, and upon receipt of an acknowledgement of the packet accompanied by a packet identifier from a receiving station, the packet associated with the packet identifier is removed from the block buffer.

Abstract: An apparatus, system, and method are disclosed for phased array antenna communications. A phased array antenna tile includes a plurality of antenna elements. A beamformer module is integrated into the phased array antenna tile. The beamformer module is electrically coupled to each antenna element to process directional signals for the plurality of antenna elements. A plurality of cascadable connection points are disposed along a perimeter of the phased array antenna tile for connecting the phased array antenna tile to one or more additional phased array antenna tiles.

Abstract: A transmit-receive switch has a transmit port, an antenna port, and a receive port. A first switch couples the transmit port to the antenna port when a signal TxON is asserted. A LOW_BAND signal indicates the selection of a lower band of frequencies. A tuning structure is formed by a second and third switch in series which couple the antenna port to ground through a first capacitor when TxON and LOW_BAND are both asserted, and LOW_BAND may be provided to one or more such tuning structures for multi-band frequency operation. A second capacitor couples the antenna port to ground when a fourth switch is enabled. An inductor couples the antenna port to the receive port. A third capacitor is placed across the receive port and ground. A fifth switch is closed when TxON is asserted. The first through fifth switches can be a CMOS FET with an isolated substrate coupled to ground through an associated resistor.

Abstract: A wireless receiver generates quadrature baseband signals which are sampled by a high speed analog to digital converter (IQ ADC) and also uses a receive signal strength indicator (RSSI) which is sampled by an RSSI analog to digital converter (RSSI ADC). The RSSI ADC signal is processed in combination with an end of packet signal to generate a first threshold from the average RSSI signal after the end of packet with the receive amplifiers set to a comparatively high level. A second threshold is generated by adding a threshold increment to the first threshold, and when the RSSI crosses the second threshold, the IQ ADC is taken out of a standby mode and placed in an active mode for the duration of the packet. The RSSI ADC is enabled from end of packet until packet detection by the baseband processor, and placed in standby at other times.

Abstract: A Reed Solomon decoder utilizes re-configurable and re-usable components in a granular configuration which provides an upper array and a lower array of repeated Reconfigurable Elementary Units (REU) which in conjunction with a FIFO can be loaded with syndromes and correction terms to decode Reed Solomon codewords. The upper array of REUs and lower array of REUs handle the Reed Solomon decoding steps in a pipelined manner using systolic REU structures. The repeated REU includes the two registers, two Galois Field adders, a Galois Field multiplier, and multiplexers to interconnect the elements. The REU is then able to perform each of the steps required for Reed-Solomon decoder through reconfiguration for each step using the multiplexers to reconfigure the functions. In this manner, a reconfigurable computational element may be used for each step of the Reed-Solomon decoding process.

Abstract: A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received subcarriers by forming candidate values based on the received subcarriers in combination with possible integer preamble offsets and possible preamble values. A candidate evaluator selects which of the possible preamble values and integer frequency offset values have the maximum CINR, and provides the maximum CINR with IFO and preamble index as outputs.

Abstract: An in-order issue in-order completion micro-controller comprises a pipeline core comprising in succession a fetch address stage, a program access stage, a decode stage, a first execution stage, a second execution stage, a memory access stage, and a write back stage. The various stages are provided a thread ID such that alternating stages use a first thread ID, and the other stages use a second thread ID. Each stage which requires access to thread ID specific context information uses the thread ID to specify this context information.

Abstract: A traffic radar utilizes digital signal processing (DSP) to determine targets based on signal strength histories. From these histories, a target vehicle having the strongest Doppler return signal is identified and its speed is displayed, and a target vehicle having the highest frequency return signal is identified and its speed is displayed. The traffic radar may also display the relative strength of the strongest return signal and the relative strength of the highest frequency return signal, thereby showing a comparison of the strengths of the return signals from the target vehicles.

Abstract: The present inventors compared myocardial damages after ischemia/reperfusion in wild-type mice and Midkine (MK)-deficient mice to confirm the effects and functions of MK. MK administration was found to significantly prevent cardiomyocyte apoptosis in both cultured cardiomyocytes (in vitro) and mouse models (in vivo).

Abstract: A wireless signal processor includes an analog front end for generating at least one baseband analog signal, at least one analog to digital converter for converting the baseband signal into a digital signal, the analog to digital converter having a resolution width and a sampling rate, and a baseband processor for measuring the signal energy in the analog to digital converter output, and when the incoming signal energy level increases or a baseband processor detects a packet, at least one of the sampling rate or resolution width also increases until the end of the packet, after which the sample rate and resolution are reduced to an interpacket rate and resolution. Additionally, the sampling rate and resolution increase after packet detection at rates and resolutions which are dependent on packet type and data rate.

Abstract: An interrupt controller for a dual thread processor has for a first thread, an interrupt request register accessible to the second thread, an interrupt count accessible to the second thread, and an interrupt acknowledge accessible to the first thread. Additionally, the interrupt controller has, for a second thread, an interrupt request register accessible to the first thread, an interrupt count accessible to the first thread, and an interrupt acknowledge accessible to the second thread. Each interrupt controller separately has a counter for each request which increments upon assertion of a request and decrements upon assertion of an acknowledgement.

Abstract: A switch machine that includes a first relay having first normally open contacts and first normally closed contacts provided in the normal motor connection path and a second relay having second normally open contacts and second normally closed contacts provided in the reverse motor connection path. The normally open and closed contacts of each relay are associated in pairs and the first relays are structured such that each normally closed contact and the corresponding normally open contact cannot be simultaneously closed. Also, a method of protecting a motor of a switch machine that includes integrating a current being drawn by the motor and opening a motor circuit that includes the motor if the integrated current exceeds a threshold.

Abstract: A SINR estimator receiving a symbol stream has a delay element coupled to the symbol stream to produce a delayed symbol stream, which is also coupled to a conjugator. A first multiplier forms a product from the symbol stream and the output of the conjugator, thereafter summing these values over an interval L and scaling by L to form a correlated power estimate Cn. A second multiplier forms a product from the symbol stream which is multiplied by the conjugate of the input, thereafter summing these values over the preamble interval 2L and scaling by 2L to form a non-correlated power estimate Pn. Cn and Pn are compared to generate an SINR estimate.