Abstract: A quasi-resonant auto-tuning controller includes a zero-voltage crossing detection circuit and a valley tuning finite-state machine having a look-up table. The zero-voltage crossing detection circuit receives a reference voltage and receives an auxiliary signal from an auxiliary winding. The zero-voltage crossing detection circuit produces a comparison signal having pulses when the auxiliary signal is less than the reference voltage. The valley tuning finite-state machine produces a divided pulse width based on the comparison signal, stores the divided pulse width of each pulse in the look-up table, determines, from the comparison signal, that the auxiliary signal is less than the reference voltage, waits a time period corresponding to the divided pulse width stored in the look-up table if the auxiliary signal is less than the reference voltage, and produces a valley point signal after waiting the time period.

Abstract: A pulsed laser diode driver includes a source capacitor that receives a refresh current at a first terminal and develops a source voltage therefrom. A first terminal of an inductor is connected to the first terminal of the source capacitor. A second terminal of the inductor is connected to an anode of a laser diode and a bypass capacitor. One or more switches are configured to control a current flow through the inductor. A timing and control circuit is configured to receive the source voltage and to generate one or more gate driver signals to control the switches to produce a high-current pulse through the laser diode. The high-current pulse corresponds to a peak current of a resonant waveform developed at the anode of the laser diode. A timing of the one or more gate driver signals is based on a voltage level of the source voltage.

Abstract: A pulsed laser diode driver includes multiple resonant laser diode driver cells, each cell including an inductor having a first inductor terminal to receive a source voltage, a source capacitor coupled between the first inductor terminal and ground, a bypass capacitor having a first terminal connected to the first inductor terminal and a second terminal connected to a second inductor terminal, a laser diode having a cathode that is connected to the first inductor terminal and an anode that is connected to the second inductor terminal, and a bypass switch connected between the second inductor terminal and ground. Each cell's bypass switch is configured to control a current flow through that cell's respective inductor to produce a high-current pulse through that cell's laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of that cell's laser diode.

Abstract: A pulsed laser diode driver includes a laser diode switch and a bypass switch to control a current flow through an inductor to produce a high-current pulse through a laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at an anode of the laser diode. A current pulse measurement circuit receives a sense voltage developed at a sense resistance and generates, based on the sense voltage, a current sense signal that corresponds to the peak current amplitude of the high-current pulse through the laser diode.

Abstract: A pulsed laser diode driver includes a refresh circuit configured to generate a refresh current using a received input voltage. A current amplitude of the refresh current is controlled by the refresh circuit based on a voltage level of a source voltage received by the refresh circuit. A source capacitor of the pulsed laser diode driver is configured to receive the refresh current and to develop the source voltage therefrom. An inductor of the pulsed laser diode driver has a first terminal that is directly electrically connected to the source capacitor. One or more switches of the pulsed laser diode driver are configured to control a current flow through the inductor to produce a high-current pulse through a laser diode that corresponds to a peak current of a resonant waveform developed at an anode of the laser diode.

Abstract: A multi-port charger includes two or more integrated power delivery modules electrically coupled to an AC-to-DC power converter. Each of the integrated power delivery modules includes a module controller in signal communication with a digital communication bus, a USB-PD controller, a switch-mode DC-to-DC power converter which is configured to provide an adjustable output voltage to a sink device via a USB voltage bus, a first analog-to-digital converter (ADC) circuit in signal communication with the USB-PD controller and the USB voltage bus to generate a digital representation of the output voltage, and a second ADC circuit in signal communication with the USB-PD controller and the USB voltage bus to provide a digital representation of an output current provided by the switch-mode DC-to-DC power converter to the sink device.

Abstract: A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.

Abstract: A power converter includes a transformer having a primary-side winding connected to a switch, and a controller connected to a gate node of the switch. The controller includes a switch timing and control module to generate switch control pulses, a gate driver to receive the switch control pulses and generate gate control pulses therefrom to control the switch, and a gate drive controller to provide a switch transition speed control signal to the gate driver to control a switch transition speed of the switch for each pulse of the gate control pulses. Based on an operating mode of the power converter, the gate drive controller is configured to set the switch transition speed of the gate driver to a first speed for generating an initial gate control pulse and to set the switch transition speed of the gate driver to a second speed for generating subsequent gate control pulses.

Abstract: An improved ramp generator enables a very high degree of linearity in an output voltage ramp signal. Output ramps of the output voltage ramp signal are alternatingly produced from two preliminary ramp signals during alternating time periods. Preliminary ramps are produced at different preliminary ramp nodes that are alternatingly connected to an output node. The preliminary ramps continuously ramp during and in some cases beyond, e.g., before and/or after, the time periods. In some embodiments, switches alternatingly connect two capacitors to at least one current source, a reset voltage source, and the output node to alternatingly produce the preliminary ramps.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.

Abstract: An apparatus for turning off a cascode amplifier having a common-base transistor and a common-emitter transistor is disclosed that includes the cascode amplifier, a feedback circuit, and a bias circuit. The feedback circuit is configured to receive a collector-voltage from the collector of the common-emitter transistor when the common-emitter transistor is switched to a first OFF state and produce a first feedback signal. The collector-voltage is equal to a emitter voltage of the common-base transistor and the collector-voltage increases in response to switching the common-emitter transistor to the first OFF state. The bias circuit is configured to receive the first feedback signal and produce a bias-voltage. A first base-voltage is produced from the bias-voltage. The cascode amplifier is configured to receive the first base-voltage and a second base-voltage. The common-base transistor is configured to switch to a second OFF state in response to receiving the second base-voltage.

Abstract: A laser diode driver includes a clock terminal to receive a clock signal, configuration terminals to receive configuration data, drive terminals, and charging terminals. A first charging terminal is operable to charge a source capacitor of a resonant circuit that includes the source capacitor, an inductor, and a bypass capacitor. Each drive terminal is operable to be directly electrically connected to an anode or cathode of a laser diode or to ground. A mode, output selection, and grouping of drive signals that are delivered to the laser diodes are configured based on the configuration data. The laser diode driver is operable to control a current flow through the resonant circuit to produce high-current pulses through the laser diodes, the high-current pulses corresponding to a peak current of a resonant waveform developed at respective anodes of the laser diodes, a timing of the high-current pulses being synchronized using the clock signal.

Abstract: An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.

Abstract: A power converter includes a transformer having a primary-side winding connected to a switch, and a controller connected to a gate node of the switch. The controller includes a switch timing and control module to generate switch control pulses, a gate driver to receive the switch control pulses and generate gate control pulses therefrom to control the switch, and a gate drive controller to provide a switch transition speed control signal to the gate driver to control a switch transition speed of the switch for each pulse of the gate control pulses. Based on an operating mode of the power converter, the gate drive controller is configured to set the switch transition speed of the gate driver to a first speed for generating an initial gate control pulse and to set the switch transition speed of the gate driver to a second speed for generating subsequent gate control pulses.

Abstract: A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: A pulsed laser diode driver includes an inductor having a first terminal to receive a source voltage, and a second terminal, a source capacitor coupled between the first terminal of the inductor and ground, a bypass capacitor having a first terminal connected to the first terminal of the inductor and a second terminal connected to the second terminal of the inductor, a laser diode having a cathode that is connected to the first terminal of the inductor and an anode that is connected to the second terminal of the inductor, and a bypass switch connected between the second terminal of the inductor and ground. The bypass switch is configured to control a current flow through the inductor to produce a high-current pulse through the laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of the laser diode.

Abstract: A pulsed laser diode driver includes multiple resonant laser diode driver cells, each cell including an inductor having a first inductor terminal to receive a source voltage, a source capacitor coupled between the first inductor terminal and ground, a bypass capacitor having a first terminal connected to the first inductor terminal and a second terminal connected to a second inductor terminal, a laser diode having a cathode that is connected to the first inductor terminal and an anode that is connected to the second inductor terminal, and a bypass switch connected between the second inductor terminal and ground. Each cell's bypass switch is configured to control a current flow through that cell's respective inductor to produce a high-current pulse through that cell's laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of that cell's laser diode.

Abstract: In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.