Abstract: A pulsed laser diode array driver includes an inductor having a first terminal configured to receive a source voltage, a source capacitor coupled between the first terminal of the inductor and ground, a bypass capacitor connected between a second terminal of the inductor and ground, a bypass switch connected between the second terminal of the inductor and ground, a laser diode array with one or more rows of laser diodes, and one or more laser diode switches, each being connected between a respective row node of the laser diode array and ground. The laser diode switches and the bypass switch are configured to control a current flow through the inductor to produce respective high-current pulses through each row of the laser diode array, each of the high-current pulses corresponding to a peak current of a resonant waveform developed at that row of the laser diode array.

Abstract: A pulsed laser diode driver includes an inductor having a first terminal configured to receive a source voltage. A source capacitor has a first terminal connected to the first terminal of the inductor to provide the source voltage. A bypass switch has a drain node connected to a second terminal of the inductor and to a first terminal of a bypass capacitor. A laser diode switch has a drain node connected to the second terminal of the inductor. A laser diode has an anode connected to a source node of the laser diode switch and a cathode connected to a bias voltage node. The laser diode switch and the bypass switch control a current flow through the inductor to produce a high-current pulse through the laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of the laser diode.

Abstract: A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced.

Abstract: A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.

Abstract: A pulsed laser diode driver includes an inductor having a first terminal configured to receive a source voltage. A source capacitor has a first terminal connected to the first terminal of the inductor to provide the source voltage. A bypass switch has a drain node connected to a second terminal of the inductor and to a first terminal of a bypass capacitor. A laser diode switch has a drain node connected to the second terminal of the inductor. A laser diode has an anode connected to a source node of the laser diode switch and a cathode connected to a bias voltage node. The laser diode switch and the bypass switch control a current flow through the inductor to produce a high-current pulse through the laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of the laser diode.

Abstract: A power converter includes a transformer having a primary-side winding connected to a switch, and a controller connected to a gate node of the switch. The controller includes a switch timing and control module to generate switch control pulses, a gate driver to receive the switch control pulses and generate gate control pulses therefrom to control the switch, and a gate drive controller to provide a switch transition speed control signal to the gate driver to control a switch transition speed of the switch for each pulse of the gate control pulses. Based on an operating mode of the power converter, the gate drive controller is configured to set the switch transition speed of the gate driver to a first speed for generating an initial gate control pulse and to set the switch transition speed of the gate driver to a second speed for generating subsequent gate control pulses.

Abstract: A pulsed laser diode driver includes a refresh circuit configured to generate a refresh current using a received input voltage. A current amplitude of the refresh current is controlled by the refresh circuit based on a voltage level of a source voltage received by the refresh circuit. A source capacitor of the pulsed laser diode driver is configured to receive the refresh current and to develop the source voltage therefrom. An inductor of the pulsed laser diode driver has a first terminal that is directly electrically connected to the source capacitor. One or more switches of the pulsed laser diode driver are configured to control a current flow through the inductor to produce a high-current pulse through a laser diode that corresponds to a peak current of a resonant waveform developed at an anode of the laser diode.

Abstract: A power converter includes an AC/DC converter to generate a DC output voltage based on an AC input voltage. A multi-port DC output circuit receives the DC output voltage and provides respective DC output voltages to a first DC output port and a second DC output port. The multi-port DC output circuit includes a first intermediate rail voltage switch, a second intermediate rail voltage switch, and multiple bus switches, a body diode of the first intermediate rail voltage switch being forward biased with respect to the first secondary side output voltage, and a body diode of the second intermediate rail voltage switch being reverse biased with respect to the first secondary side output voltage. The bus switches control a routing of a first intermediate rail voltage and a second intermediate rail voltage of the multi-port DC output circuit to the first DC output port and the second DC output port.

Abstract: A transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.

Abstract: A power converter includes a transformer, a main switch, an active clamp switch, and a primary side controller circuit. The primary side controller circuit is configured to indirectly measure a magnetizing current through the transformer during a first switching cycle of the power converter and estimate a zero-crossing point of the magnetizing current for a second switching cycle based on the indirect primary side measurement of the magnetizing current. Based on the estimated zero-crossing point, the primary side controller circuit generates an auto-tuned delay, for the second switching cycle, between disabling the main switch and enabling the active clamp switch before the zero-crossing of the magnetizing current occurs. The active clamp switch is enabled during the second switching cycle in accordance with the auto-tuned delay.

Abstract: An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.

Abstract: A multi-port charger includes two or more integrated power delivery modules electrically coupled to an AC-to-DC power converter. Each of the integrated power delivery modules includes a module controller in signal communication with a digital communication bus, a USB-PD controller, a switch-mode DC-to-DC power converter which is configured to provide an adjustable output voltage to a sink device via a USB voltage bus, a first analog-to-digital converter (ADC) circuit in signal communication with the USB-PD controller and the USB voltage bus to generate a digital representation of the output voltage, and a second ADC circuit in signal communication with the USB-PD controller and the USB voltage bus to provide a digital representation of an output current provided by the switch-mode DC-to-DC power converter to the sink device.

Abstract: A pulsed laser diode array driver includes an inductor having a first terminal configured to receive a source voltage, a source capacitor coupled between the first terminal of the inductor and ground, a bypass capacitor connected between a second terminal of the inductor and ground, a bypass switch connected between the second terminal of the inductor and ground, a laser diode array with one or more rows of laser diodes, and one or more laser diode switches, each being connected between a respective row node of the laser diode array and ground. The laser diode switches and the bypass switch are configured to control a current flow through the inductor to produce respective high-current pulses through each row of the laser diode array, each of the high-current pulses corresponding to a peak current of a resonant waveform developed at that row of the laser diode array.

Abstract: An apparatus for turning off a cascode amplifier having a common-base transistor and a common-emitter transistor is disclosed that includes the cascode amplifier, a feedback circuit, and a bias circuit. The feedback circuit is configured to receive a collector-voltage from the collector of the common-emitter transistor when the common-emitter transistor is switched to a first OFF state and produce a first feedback signal. The collector-voltage is equal to a emitter voltage of the common-base transistor and the collector-voltage increases in response to switching the common-emitter transistor to the first OFF state. The bias circuit is configured to receive the first feedback signal and produce a bias-voltage. A first base-voltage is produced from the bias-voltage. The cascode amplifier is configured to receive the first base-voltage and a second base-voltage. The common-base transistor is configured to switch to a second OFF state in response to receiving the second base-voltage.

Abstract: A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.

Abstract: A pulsed laser diode driver includes a laser diode package having a first anode terminal, a cathode terminal, a laser diode, a first bond wire, and a second bond wire. A cathode of the laser diode is electrically connected to the cathode terminal, an anode of the laser diode is electrically connected to a first end of the first bond wire and to a first end of the second bond wire. A second end of the first bond wire is electrically connected to the first anode terminal, and a second end of the second bond wire is electrically connected to a capacitor. One or more switches are configured to control a current flow through the first and second bond wires to produce a high-current pulse through the laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of the laser diode.

Abstract: A multi-port charger includes two or more integrated power delivery modules electrically coupled to an AC-to-DC power converter. Each of the integrated power delivery modules includes a module controller in signal communication with a digital communication bus, a USB-PD controller, a switch-mode DC-to-DC power converter which is configured to provide an adjustable output voltage to a sink device via a USB voltage bus, a first analog-to-digital converter (ADC) circuit in signal communication with the USB-PD controller and the USB voltage bus to generate a digital representation of the output voltage, and a second ADC circuit in signal communication with the USB-PD controller and the USB voltage bus to provide a digital representation of an output current provided by the switch-mode DC-to-DC power converter to the sink device.

Abstract: A pulsed laser diode array driver includes an inductor having a first terminal configured to receive a source voltage, a source capacitor coupled between the first terminal of the inductor and ground, a bypass capacitor connected between a second terminal of the inductor and ground, a bypass switch connected between the second terminal of the inductor and ground, a laser diode array with one or more rows of laser diodes, and one or more laser diode switches, each being connected between a respective row node of the laser diode array and ground. The laser diode switches and the bypass switch are configured to control a current flow through the inductor to produce respective high-current pulses through each row of the laser diode array, each of the high-current pulses corresponding to a peak current of a resonant waveform developed at that row of the laser diode array.

Abstract: A regenerative gate charging circuit includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first timing profile, and transmits the output control signals to the output control circuit. In accordance with the first timing profile, the output control circuit holds switches or controllable current sources of the bridged inductor driver in an ON state for a first period and holds the switches or controllable current sources in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second timing profile using the sampled voltages.

Abstract: A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.