Patents Assigned to Silergy Semiconductor Technology (Hangzhou) Ltd.
  • Patent number: 11038424
    Abstract: A DC-DC converter can include: a switched capacitor converter including at least one switch group and at least one capacitor, where each switch group includes two switches coupled in series, and at least one capacitor is respectively coupled in parallel with a corresponding one of the switch groups; and a switch converter including a first magnetic component, where the switch converter is configured to share one of the switch groups, the first magnetic component is coupled to an intermediate node of the shared switch group, and the intermediate node is a common coupling point of two switches of the shared switch group.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: June 15, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Chen Zhao, Wang Zhang
  • Patent number: 11031388
    Abstract: A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first and second regions; an isolation structure located in the isolation region, where the isolation structure comprises a first isolation ring having a first doping type, and a second isolation ring having a second doping type, where the first isolation ring is configured to absorb first carriers flowing from the first region to the second region, and where the second isolation ring is configured to absorb second carriers flowing from the second region to the first region; and a lateral blocking component in the isolation structure, where the lateral blocking component is configured to block a lateral flow of the first and second carriers, in order to increase a flow path of the first and second carriers in the semiconductor substrate.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 8, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Yicheng Du, Meng Wang, Hui Yu
  • Patent number: 11031497
    Abstract: A semiconductor device can include: a substrate having a first doping type; a first well region located in the substrate and having a second doping type, where the first well region is located at opposite sides of a first region of the substrate; a source region and a drain region located in the first region, where the source region has the second doping type, and the drain region has the second doping type; and a buried layer having the second doping type located in the substrate and below the first region, where the buried layer is incontact with the first well region, where the first region is surrounded by the buried layer and the first well region, and the first doping type is opposite to the second doping type.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 8, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Meng Wang, Yicheng Du, Hui Yu
  • Publication number: 20210166999
    Abstract: A chip package assembly and a method for manufacturing the same are provided. A die is attached to one of pins located around a chip carrier, so that an electronic component such as a diode is packaged in the chip package assembly and is electrically connected in series with other dies inside the package, thereby improving the degree of integration of the chip package assembly, and reducing a volume of the external circuit.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Applicant: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
    Inventor: Shijie CHEN
  • Patent number: 11026308
    Abstract: A power converter can include: a rectifier circuit; a silicon controlled dimmer coupled between an AC input terminal and an input terminal of the rectifier circuit; and a bleeder circuit coupled to an output terminal of the rectifier circuit, and being configured to provide a bleeder current after the silicon controlled dimmer is turned off. A method of controlling a power converter, can include: generating a bleeder current flowing though output terminals of a rectifier circuit of the power converter after a silicon controlled dimmer is turned off; and where the silicon controlled dimmer coupled to the rectifier circuit receives an AC input voltage.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: June 1, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Huiqiang Chen, Zhishuo Wang, Jianxin Wang
  • Patent number: 11022992
    Abstract: A voltage regulator can include: an input port with two terminals, and being configured to receive an input voltage; an output port with two terminals, and being configured to generate an output voltage, where the input port and the output port have a common ground potential; a group of input switches coupled in series between the two terminals of the input port, where a common node of every two adjacent input switches that form an input half-bridge topology is taken as an input switch node; at least one output half-bridge topology coupled between two terminals of the output port, where a common node of a high-side output switch and a low-side output switch in each output half-bridge topology is taken as an output switch node; and N storage capacitors, where each of the storage capacitors is coupled between one input switch node and one output switch node.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 1, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Wang Zhang, Chen Zhao, Lang Mao
  • Patent number: 11018590
    Abstract: A control circuit for a flyback converter is configured to adjust a conduction time of an auxiliary switch of the flyback converter in accordance with a drain-source voltage of a main switch of the flyback converter when the main switch is turned on, in order to achieve zero-voltage switching of the main switch. The flyback converter can include: a main power stage having the main switch to control energy storage and transmission of a transformer; and a clamp circuit having an auxiliary switch to provide a release path for releasing energy of leakage inductance of the transformer.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 25, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Xiangdong Yang, Xiaoru Xu, Yongjiang Bai, Zhiliang Hu
  • Patent number: 10998305
    Abstract: A semiconductor die can include: first, second, third, and fourth transistors disposed at intervals, where each two of the first, second, third, and fourth transistors are separated by a separation region to form four separation regions; an isolation structure having a first doping structure of a first doping type, and a second doping structure of a second doping type, to absorb hole carriers and electron carriers flowing between the first, second, third, and fourth transistors; where the first doping structure is located in the separation region to isolate adjacent transistors in the first, second, third, and fourth transistors; and where at least a portion of the second doping structure is surrounded by the first doping structure, and the second doping structure is separated from the first doping structure.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 4, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Jianping Qiu, Yicheng Du, Meng Wang
  • Patent number: 10996390
    Abstract: A light guide plate can include: a first end surface coupled to a reflection surface and a second end surface; where an incident light entering the light guide plate through the first end surface is reflected by the reflection surface and then output from the second end surface; and a diffusion structure configured to increase a transmission path of the incident light in the light guide plate.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: May 4, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Suyi Lin
  • Patent number: 10998416
    Abstract: A laterally diffused metal oxide semiconductor device can include: a well region having a second doping type; a reduced surface field effect layer of a first doping type formed by an implantation process in a predetermined region of the well region, where a length of the reduced surface field effect layer is less than a length of the well region; a body region of the first doping type extending from a top surface of the well region into the well region; a drain portion of the second doping type extending from the top surface of the well region into the well region; and an insulating structure located between the body region and the drain portion, at least a portion of the insulating structure is located on the top surface of the well region.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 4, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Budong You, Hui Yu, Meng Wang, Yicheng Du, Chuan Peng, Xunyi Song
  • Patent number: 10985052
    Abstract: A method of cleaning a contact hole of a semiconductor device, can include: removing a first portion of an object to be removed in the contact hole by a dry cleaning process, where a second portion of the object to be removed remains after the dry cleaning process has completed; and removing the second portion of the object to be removed by a wet cleaning process. The method can further include: forming an interlayer dielectric layer on a semiconductor substrate having a contact region; etching the interlayer dielectric layer to form the contact hole, where the contact hole penetrates the interlayer dielectric layer and exposes the contact region; and after the cleaning of the contact hole, filling the contact hole by a metal material to form a metal plug that is in contact with the contact region.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: April 20, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Huan Wang
  • Patent number: 10978441
    Abstract: Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer is introduced based on the prior transient voltage suppressor, and the diffusion isolation regions are reused as the conductive vias, so that, the gate stack layer, the first doped region, the conductive vias, and the second semiconductor layer constitute a MOS transistor being coupled in parallel to the Zener diode or the avalanche diode of the transient voltage suppressor. When the current of the I/O terminal is relatively large, the MOS transistor is turned on to share part of the current of the I/O terminal through the Zener diode or the avalanche diode, thereby protecting the Zener diode or the avalanche diode from being damaged due to excessive current. Thus, the robustness of the transient voltage suppressor is improved without increasing the manufacture cost.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 13, 2021
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: Dengping Yin, Shijun Wang, Fei Yao
  • Patent number: 10971437
    Abstract: A chip package structure can include: a lead frame having a plurality of pins, a first die pad, and a second die pad; a first die and a second die, where a first surface of the first die is installed on the first die pad, and a first surface of the second die is installed on the second die pad; a plurality of pads installed on a second surface of the first die and a second surface of the second die; and bonding wires including a first set of bonding wires with each having one terminal connected to pads of the first die, and a second set of bonding wires with each having one terminal connected to pads of the second die for connectivity between the first die and the second die, and between the plurality of pins and the first die and the second die.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: April 6, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Shijie Chen
  • Patent number: 10965283
    Abstract: An apparatus can include: a drive circuit for a floating switch having first and second transistors coupled in series, where gate terminals of the first and second transistors are coupled together, and source terminals of the first and second transistors are coupled together; a control circuit coupled to the gate terminals of the first and second transistors, and being configured to control on and off states of the first and second transistors; and a clamp circuit configured to clamp gate-source voltages of the first and second transistors to maintain current switching states of the first and second transistors.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 30, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Xiaoming Duan, Jun Chen
  • Patent number: 10958178
    Abstract: The disclosure relates to a control circuit, a control method and a flyback converter of primary-side feedback control including the control circuit. When an input voltage is greater than a predetermined threshold, a peak value of an input current of the flyback converter is controlled to vary with the input voltage by the switching control signal. When the input voltage is less than the predetermined threshold, the peak value of the input current is controlled to be increased by the switching control signal to make demagnetization time of a secondary winding of the flyback converter be greater than a minimum time. Thus, the peak value of the primary-side current may not become too small because of a decreased input voltage, further avoiding occurrence of an error sampling after a blanking time due to excessive variations in demagnetization time.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 23, 2021
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: Huiqiang Chen, Jianxin Wang
  • Patent number: 10951050
    Abstract: An adaptive charger can include: a power converter configured to receive an input current from an external power supply, and to generate an output current as a charging current to a load; a current feedback loop configured to compare a first detection signal that represents the input current against a first current reference signal, and to generate a first error signal, where the power converter is configured to regulate the input current according to the first error signal; and the current feedback loop being configured to determine an overload state of the external power supply according to an input voltage of the power converter, where the charger is configured to enter a current limit state when the external power supply is determined to be in the overload state, and where the first current reference signal is gradually reduced until the external power supply recovers to a non-overloaded state.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 16, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Shuai Cheng
  • Patent number: 10951120
    Abstract: The disclosure relates to a flyback converter, a control circuit and a control method therefor. In the control method, a power stage circuit is controlled at a light load to operate alternatively in a pulse-width modulation mode (e.g., a constant switching frequency mode) and in a constant on time mode, in accordance with a voltage compensation signal. Thus, output energy may decrease rapidly and smoothly, without need for the control circuit to stop working. The flyback converter has increased efficiency at the light load and decreased output voltage ripple.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: March 16, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Huiqiang Chen
  • Patent number: 10950528
    Abstract: A chip package assembly and a method for manufacturing the same are provided. A die is attached to one of pins located around a chip carrier, so that an electronic component such as a diode is packaged in the chip package assembly and is electrically connected in series with other dies inside the package, thereby improving the degree of integration of the chip package assembly, and reducing a volume of the external circuit.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: March 16, 2021
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
    Inventor: Shijie Chen
  • Publication number: 20210068231
    Abstract: A current source circuit and an LED driving circuit applying the same. A current at an output terminal of an operational transconductance amplifier is shunted based on a first control signal that includes duty cycle information, or an input signal at at least one input terminal of the operational transconductance amplifier is controlled to be switched between different voltage signals based on the first control signal, so as to adjust an output current of a current adjustment circuit. A driving voltage for driving a current generation circuit is adjusted based on the output current. Thereby, a driving current generated by the current source circuit is correlated with the duty cycle information. An amplitude modulation circuit used, a low-pass filter and the like for processing the first control signal are not used, effectively simplifying circuit design and improving system efficiency.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Applicant: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
    Inventor: Hao CHEN
  • Patent number: 10928047
    Abstract: A package for a power supply circuit and an LED illumination module are provided. The package includes: a first package body, configured to package a power device, a control chip and a passive element; an inductive element; a connector configured to connect an electrode of the inductive element to a corresponding electrode of the power device; an encapsulant configured to encapsulate the first package body, the inductive element and the connector; and multiple pins exposed through the encapsulant and configured to achieve external electrical connection. In the package, the control chip, the inductive element and the passive element are packaged together, thereby reducing an area occupied by the drive circuit in the LED illumination module.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 23, 2021
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
    Inventors: Wei Chen, Jian Wei