Patents Assigned to Silicon Bandwidth Inc.
  • Publication number: 20040010638
    Abstract: A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.
    Type: Application
    Filed: April 1, 2003
    Publication date: January 15, 2004
    Applicant: Silicon Bandwidth, Inc.
    Inventor: Stanford W. Crane
  • Patent number: 6663294
    Abstract: Optoelectronic packaging assemblies for optically and electrically interfacing an electro-optical device to an optical fiber and to external circuitry. An optoelectronic packaging assembly includes a submount for holding an optical bench with an electro-optical device. Electrically conductive pins provide electrical contact to the electro-optical device. The optoelectronic packaging assembly includes an optical input receptacle for receiving an optical ferrule and an optical fiber. The optical input receptacle assists optical coupling of the electro-optical device to the optical fiber. The optoelectronic packaging assembly provides for cooling using a heat-sink or a thermal-electric-cooler. Beneficially, the optoelectronic packaging assembly is sealed using a cover.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: December 16, 2003
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Zsolt Horvath
  • Publication number: 20030162319
    Abstract: A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.
    Type: Application
    Filed: February 26, 2002
    Publication date: August 28, 2003
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Vicente D. Alcaria, Myoung-Soo Jeon
  • Patent number: 6603193
    Abstract: A semiconductor package having a molded body and a plurality of conductive pins that extend from the bottom of the molded body. The semiconductor package further includes a RF shield around a protected cavity that holds a first integrated circuit. The molded body can further include an unprotected plastic cavity for holding a second integrated circuit. The conductive pins form bonding pads that are used to electrically interconnect the first and second semiconductor devices to the external environment. A cover, beneficially comprised of copper, is disposed over the molded body. The plastic cavity beneficially includes a beveled wall that improves the routing of electrical conductors between the first integrated circuit and the second integrated circuit.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: August 5, 2003
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Myoung-Soo Jeon, Vicente D. Alcaria
  • Patent number: 6577003
    Abstract: A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: June 10, 2003
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Maria M. Portuondo
  • Patent number: 6574726
    Abstract: A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: June 3, 2003
    Assignee: Silicon Bandwidth, Inc.
    Inventor: Stanford W. Crane, Jr.
  • Publication number: 20030003626
    Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.
    Type: Application
    Filed: August 30, 2002
    Publication date: January 2, 2003
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Lakshminarasimha Krishnapura, Yun Li
  • Patent number: 6475832
    Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: November 5, 2002
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li
  • Patent number: 6461197
    Abstract: An electrical connector includes a male connector and a female connector. The female connector includes a female connector housing and a plurality of female contact pins. The female contact pins includes a contact portion, a stabilizer portion, and a tail portion. The contact portion extends from the stabilizer portion at an angle. A lateral distance spanned by the angled contact portion is substantially the same as or less than the width of the stabilizer portion in the same direction. The female contact pins are arranged on the female connector housing in clusters of four. The clusters are arranged in rows such that each pair of rows defines five rows of female contact pins. The male connector includes a male connector housing and a plurality of male contact pins. The male connector housing has a plurality of buttresses extending therefrom. The male contact pins are arranged on the male connector housing to correspond to the arrangement of female contact pins.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: October 8, 2002
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Arindum Dutta, Kevin Link
  • Publication number: 20020117751
    Abstract: A cluster grid array semiconductor die package and mating socket provide electrical connection between one or more semiconductor dies housed within the die package and substrate, such as a printed circuit board, on which the mating socket is mounted. The die package and the mating socket may be easily connected and disconnected. The die package may include power and ground planes built into and distributed within the housing of the die package.
    Type: Application
    Filed: May 31, 2001
    Publication date: August 29, 2002
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Myoung-soo Jeon, Charley Takeshi Ogata, Ton-Yong Wang, Andreas C. Cangellaris, Jose Schutt-Aine
  • Patent number: 6421254
    Abstract: A multi-chip module includes a housing having insulative side walls and an end plate, conductive leads extending from the side walls, integrated circuit (IC) dies mounted to the end plate, and one or more interconnect dies mounted to the end plate. The end plate is made from a heat sink material, such as copper. Each interconnect die is positioned between a pair of the IC dies. Electrically conductive material connects the IC dies to the interconnect die, connects the IC dies to the conductive leads, and connects the interconnect dies to the conductive leads. The interconnect dies function to interconnect the IC dies and to interconnect the IC dies to the conductive leads. The interconnect die may be embodied by wiring layers formed on a silicon substrate.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: July 16, 2002
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li, Moises Behar, Dan Fuoco, Bill Ahearn
  • Publication number: 20020053455
    Abstract: A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads.
    Type: Application
    Filed: September 28, 2001
    Publication date: May 9, 2002
    Applicant: SILICON BANDWIDTH INC.
    Inventors: Stanford W. Crane, Maria M. Portuondo
  • Publication number: 20020019174
    Abstract: An integrated module includes a connector for detachable connection to a signal source, with the connector having internal electrically conductive pins, and a housing defining a cavity for holding at least one semiconductor die. The housing includes side walls and an end plate joined to the side walls. Electrically conductive leads extend through at least one of the side walls with each of the leads including an internal lead section extending within the cavity and an external lead section extending externally of the cavity through at least one side wall. One of the side walls of the housing includes a portion that is attached to the connector, with the side walls and a bottom part of the connector being formed as one integrally molded part or as two separate parts that are joined together using processes such as ultrasonic welding.
    Type: Application
    Filed: October 16, 2001
    Publication date: February 14, 2002
    Applicant: SILICON BANDWIDTH, INC.
    Inventors: Stanford W. Crane, Lakshminarasimha Krishnapura, Arindum Dutta
  • Publication number: 20020008308
    Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.
    Type: Application
    Filed: September 13, 2001
    Publication date: January 24, 2002
    Applicant: SILICON BANDWIDTH, INC.
    Inventors: Stanford W. Crane, Lakshminarasimha Krishnapura, Yun Li
  • Patent number: 6339191
    Abstract: A semiconductor die carrier includes a plurality of electrically insulative side walls; a plurality of electrically conductive leads extending from at least one of the side walls, each of the leads being individually manufactured without use of a lead frame; a semiconductor die positioned such that the electrically conductive leads are disposed at one or more locations around the periphery of the die; and structure for providing electrical connection between the semiconductor die and corresponding ones of the electrically conductive leads.
    Type: Grant
    Filed: March 11, 1994
    Date of Patent: January 15, 2002
    Assignee: Silicon Bandwidth Inc.
    Inventors: Stanford W. Crane, Jr., Maria M. Portuondo
  • Patent number: 6334794
    Abstract: A male connector connects with a female connector to establish an electrical connection. The male and female connectors each include a connector housing having hold-down tabs at opposite ends thereof for securing the connector housing to a substrate. The hold-down tabs are staggered or diagonally located such that one hold-down tab is proximal a first side of the connector housing and the other hold-down is proximal a second side of the connector housing. The staggered or diagonally-located hold-down tabs stabilize the connector housing against rocking or other movement on the substrate. The arrangement of hold-down tabs also permits the connector housing to nest or merge with another similarly-designed connector housing. The nested or merged connector housing conserve substrate space and permit a higher density of contacts in a given space on the substrate, whether the space is at an edge or in an interior of the substrate.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: January 1, 2002
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Arindum Dutta, Kevin Link
  • Publication number: 20010034164
    Abstract: An electrical connector includes a male connector and a female connector. The female connector includes a female connector housing and a plurality of female contact pins. The female contact pins includes a contact portion, a stabilizer portion, and a tail portion. The contact portion extends from the stabilizer portion at an angle. A lateral distance spanned by the angled contact portion is substantially the same as or less than the width of the stabilizer portion in the same direction. The female contact pins are arranged on the female connector housing in clusters of four. The clusters are arranged in rows such that each pair of rows defines five rows of female contact pins. The male connector includes a male connector housing and a plurality of male contact pins. The male connector housing has a plurality of buttresses extending therefrom. The male contact pins are arranged on the male connector housing to correspond to the arrangement of female contact pins.
    Type: Application
    Filed: May 21, 2001
    Publication date: October 25, 2001
    Applicant: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Lakshminarasimha Krishnapura, Arindum Dutta, Kevin Link
  • Patent number: 6307258
    Abstract: A semiconductor die carrier includes a housing that defines a cavity for holding one or more semiconductor dies, electrically conductive leads, and a cover plate having an aperture formed therethrough. The housing includes insulative side walls and a end plate joined to the side walls. The side walls and the end plate may be molded together as a one-piece unit. One or more of the side walls includes openings for receiving the leads so that an internal lead section extends within the cavity and an external lead section extends from the side walls external of the housing. The side walls may include a recess for receiving the cover plate. The aperture in the cover plate allows a semiconductor die held in the housing to be exposed to the environment.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: October 23, 2001
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li
  • Patent number: 6305987
    Abstract: An integrated module includes a connector for detachable connection to a signal source, with the connector having internal electrically conductive pins, and a housing defining a cavity for holding at least one semiconductor die. The housing includes side walls and an end plate joined to the side walls. Electrically conductive leads extend through at least one of the side walls with each of the leads including an internal lead section extending within the cavity and an external lead section extending externally of the cavity through at least one side wall. One of the side walls of the housing includes a portion that is attached to the connector, with the side walls and a bottom part of the connector being formed as one integrally molded part or as two separate parts that are joined together using processes such as ultrasonic welding.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: October 23, 2001
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Arindum Dutta
  • Patent number: 6266246
    Abstract: A multi-chip module includes a housing having insulative side walls and an end plate, conductive leads extending from the side walls, integrated circuit (IC) dies mounted to the end plate, and one or more interconnect dies mounted to the end plate. The end plate is made from a heat sink material, such as copper. Each interconnect die is positioned between a pair of the IC dies. Electrically conductive material connects the IC dies to the interconnect die, connects the IC dies to the conductive leads, and connects the interconnect dies to the conductive leads. The interconnect dies function to interconnect the IC dies and to interconnect the IC dies to the conductive leads. The interconnect die may be embodied by wiring layers formed on a silicon substrate.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: July 24, 2001
    Assignee: Silicon Bandwidth, Inc.
    Inventors: Stanford W. Crane, Jr., Lakshminarasimha Krishnapura, Yun Li, Moises Behar, Dan Fuoco, Bill Ahearn