Abstract: A system and method for sending multiple data signals over a serial link comprises an embedding unit and a removing unit coupled by a serial line. The embedding unit preferably receives a plurality of data streams, encodes the data streams and then merges the encoded data into a serial stream that is output across a serial line to the removing unit. The removing unit receives a serial stream of data, decodes the serial stream, and then separates the decoded serial stream into separate streams thereby reconstructing the streams input to the embedding unit. The encoding and transmission by the embedding unit and the receipt and decoding by the removing unit are completely transparent, the signals output by the removing unit are identical in timing and data content to the signals input to the embedding unit. The present invention also includes a method for transmitting a plurality of data streams over a signal line, and a method for generating a plurality of data streams from a serial sequence.

Abstract: Multiple controllable delays reduce EMI radiated during the transmission of multiple synchronized signals. Each controllable delay introduces a controlled delay into a corresponding signal being transmitted. The controlled delay is such that the combined strength of the multiple signals at peak frequencies is substantially reduced. This results in reduced EMI radiation at those peak frequencies.

Abstract: A smart controller chip for controlling an active matrix display. Within the controller chip, circuitry for generating analog reference levels is incorporated alongside circuitry for generating digital timing and control signals. The combination of D/A analog circuitry and standard digital logic makes the controller uniquely suited for addressing all the panel control needs both for the normal digital functions but also for control of the analog aspects of the panel, like display gamma. The analog reference levels and the digital signals are made programmable using registers internal to the controller chip. The contents of these registers are programmed initially by digital values stored in an external PROM or in flash memory integrated into the controller chip. In addition, software in a host system is able to program these registers via an interface between the host system and the controller chip.

Abstract: To reduce the layout area required by LCD column drivers without suffering a significant decrease in performance, a PMOS-based circuit selects a voltage from an upper set of analog display voltages and a NMOS-based circuit selects a voltage from a lower set of analog display voltages. This reduces the layout area by up to roughly a factor of two compared with conventional column drivers which are CMOS-based. Moreover, in a typical dot inversion scheme, where two adjacent columns select voltages from alternating voltage sets, two adjacent columns can share the same PMOS-based and NMOS-based circuits by using multiplexers controlled by a polarity signal to route the digital display data into the sets of switches. This reduces the layout area by up to roughly an additional factor of two.

Abstract: A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity.

Abstract: A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity.

Abstract: A new high-speed digital interface for transmitting video information over various transmission media including terminated copper wires such as twisted-pair wires and fiber optical cable is described. The significance of this new interface is that (1) it only uses a small number of data channels with all timing and control data embedded in data transmission, (2) it uses a transition controlled binary DC balanced coding for reliable, low-power and high-speed data transmission, (3) it uses low-swing differential voltage which minimizes EMI, and (4) it can be implemented in low-cost scaleable CMOS technology as a megacell or standard IC. The high-speed digital interface incorporates a method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks.

Abstract: A device and method for synchronizing a local clock to a reference clock. The device uses a frequency acquisition loop and a phase acquisition loop. The frequency acquisition loop delays the reference clock to produce an intermediate clock which falls within the operating range of the phase acquisition loop. The phase acquisition loop then delays the intermediate clock to produce a local clock synchronized to the reference clock.

Abstract: A voltage-controlled oscillator (VCO) generates an oscillating signal that is substantially resistant to noise fluctuations in the supply voltage. The VCO is a delay-based VCO which preferably includes a compensation circuit for each delay cell and a noise-immune reference current generator for providing a noise-immune bias current to the conditioning circuit of the VCO. The compensation circuit preferably adjusts the capacitance of the delay cell to compensate for the variations in current caused by the supply noise. The noise-immune reference current generator preferably utilizes a configuration of transistors which maintains through at least one transistor a substantially constant current which is used to bias the conditioning circuit.

Abstract: A method and apparatus is disclosed that receives a multi-channel digital serial encoded signal and converting it signal into a synchronized set of binary characters. A charge pump phase-locked loop receives a transmitted reference clock and derives a multi-phase clock from the reference clock. The multi-phase clock is used to control a plurality of multi-bit block assembly circuits. Each assembly circuit receives one channel of the digital signal and produces a multi-bit block or character. The multi-bit block assembly circuit includes an oversampler, a digital phase-locked loop and a byte synchronizer. The oversampler oversamples the received digital signal under control of the multiphase clock and produces a sequence of oversampled binary data. The digital phase-locked loop receives the oversampled data and selects samples from it depending on the skew characteristics of the sample. The byte synchronizer assembles a sequence of selected bits into a bit block, or character.

Abstract: A system and method for sending multiple data signals over a serial link comprises an embedding unit and a removing unit coupled by a serial line. The embedding unit preferably receives a plurality of data streams, encodes the data streams and then merges the encoded data into a serial stream that is output across a serial line to the removing unit. The removing unit receives a serial stream of data, decodes the serial stream, and then separates the decoded serial stream into separate streams thereby reconstructing the streams input to the embedding unit. The encoding and transmission by the embedding unit and the receipt and decoding by the removing unit are completely transparent, the signals output by the removing unit are identical in timing and data content to the signals input to the embedding unit. The present invention also includes a method for transmitting a plurality of data streams over a signal line, and a method for generating a plurality of data streams from a serial sequence.

Abstract: A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity.

Abstract: A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal.