Abstract: The present invention relates to a serial interface transmission system with more than one data line, in which the transmitted data has in-band and out-of-band characters. More particularly, the present invention relates to methods and systems for sending side channel data over a high-speed digital communications link, e.g., a video link. One embodiment of the invention provides a high-speed digital transmitter capable of sending side channel data. The transmitter includes a channel zero encoder, a multiplexer, data enable out (DEout) control logic, and a channel one encoder. The channel one encoder receives input from the channel one multiplexer and the channel one DEout control logic. Another embodiment of the invention provides a high-speed digital receiver capable of receiving side channel data. The receiver includes a channel zero decoder, a channel one decoder, DEI signal and FIFO control signal recovery logic, and a channel one de-multiplexer.

Abstract: A system and method for measuring and utilizing a pseudo pixel error rate in digital data transmission is disclosed. As an alternative to measuring actual pixel error rate measurement, the present invention uses a pseudo pixel error rate detection scheme where the errors occurred in the special character patterns used in data encoding are measured. A particular embodiment uses a de-glitch filter for filtering the glitches from an unfiltered data enable (DE), a delay for delaying the unfiltered DE to match the delay of the de-glitch filter, and a comparator for comparing the unfiltered DE and the filtered DE to determine the occurrence of an error. It further includes a counter to count the errors occurred.

Abstract: A display module driving system wherein digital pixel data for an image to be displayed is provided to a plurality of column drivers on a row by row basis in serial format over a plurality of dedicated bus lines rather than a single parallel bus line. Digital pixel data for a complete image row is divided into segments, wherein the number of segments is each to the number of column drivers. Each segments is then serialized and transmitted to a corresponding column driver such that the digital pixel data for an entire row is transferred to each of the plurality of column drivers at the same time. The column drivers receive the segments and rearrange the data into parallel. The pixels are then transferred to a digital to analog converter, preferably two pixels at a time, where each pixel is converted into analog red, green and blue signals.

Abstract: A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively.

Abstract: A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link.

Abstract: An interlace motion artifact detector which identifies video image spatial frequencies characteristic of motion artifacts. The detected frequency is the maximum which can be represented by the vertical sampling rate of the video format (i.e., the Nyquist frequency). This frequency is detected by a pair of partial Discrete Fourier Transforms (DFT) which each calculate only the frequency component of interest. Additional vertical frequency components at one half and one quarter the interlace motion artifact frequency are also detected via a partial DFT. The presence of these lower frequencies acts as an indication of an erroneous motion artifact detection. Additionally, the dynamic range and maximum level of the video data is used as an indication of when to boost the frequency detection levels in areas of low brightness and/or contrast.

Abstract: A serial data transmission system in which a transmitter encodes data in accordance with a TMDS-like encoding algorithm and transmits the TMDS-like encoded data over a serial link to a receiver. The encoded data are transmitted as a run length limited (“RLL”) code word sequence, including transition-minimized code words. In some embodiments, the RLL code word sequence includes only Min words, including both DC balancing Min words and DC unbalancing Min words. In other embodiments, the RLL code word sequence includes both transition-maximized code words and transition-minimized code words. Other aspects of the invention are circuitry and methods for TMDS-like encoding of data for transmission as an RLL code word sequence.

Abstract: A system and a method for simple and robust baud-rate timing recovery suitable for jointly operating with a decision-feedback equalizer are disclosed. Timing functions for timing recovery are extracted only from filter coefficients of feed-forward and feedback filters. The relation between the coefficients of feed-forward filter and the impulse response is derived under a zero-forcing condition while the relation between the coefficients of the feedback filter and the impulse response is known. Based on the relations, several timing functions with varied degrees of computation are derived, which can drive the sampling instances approximately at the peak point of the channel impulse response. Since the derived timing functions use equalizer coefficients, they work jointly with equalization even without using a training sequence. Simulation results over 5-m and 100-m UTP Category-5 cables at 125M Baud show fast and robust timing recovery operation in a phase-locked loop.

Abstract: A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

Abstract: A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

Abstract: The invention relates to computer graphics and computer imaging on a video display, and includes the dynamic detection of video windows and graphical images overlapping one another. A display processor identifies differences between typical video and graphics data sources to detect the edges of video windows. By detecting the edges of active video windows within a graphics image, a display processor may uniquely adjust image characteristics of an exposed video window. These characteristics include, for example, hue, brightness, intensity and contrast.

Abstract: The present invention is directed to systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of: a) performing transition controlled encoding of a first sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to produce masked n+1 bit data characters; c) DC balancing the masked n+1 bit data characters to produce DC balanced, masked n+2 bit data characters; d) scrambling the DC balanced, masked n+2 bit data characters using a scrambling formula to produce encrypted n+2 bit data characters; e) encoding control data into encoded n+2 bit control characters, f) generating a serial data stream in response to the encrypted data characters and encoded control characters, and g) transmitting the serial data stream over a communication link.

Abstract: A deinterlacing system which converts an interlaced video stream into a progressive video stream is disclosed. The deinterlacing system includes a field assembly responsive to a last field, a next field, a current field and progressive source phase and operative to develop a progressive output frame, a source detection module responsive to last, next and current fields and operative to develop a progressive source phase and a progressive source detected and an intra-frame deinterlacer responsive to the progressive output frame and the progressive source detected and operative to develop a progressive frame output.

Abstract: A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.

Abstract: A method for connecting to an SATA storage component includes a chassis having an interior and an exterior, and a wall portion provided with an opening. An SATA compatible connector, provided with a first restraining flange and a second restraining flange spaced from the first restraining flange, is inserted into the opening in the wall portion, wherein an interior surface of the first restraining flange faces a first surface of the wall portion and an interior surface of the second restraining flange faces a second surface of the wall portion. An SATA storage component is then inserted into the chassis such that it connects with the SATA compatible connector, whereby the first and second flange allows the SATA compatible connector to float in a limited fashion within the opening.

Abstract: A system and method for embedding at least one clock signal into bus lines that also carry data signals at other times to enable a high-speed bus is disclosed. Each bus line is used for carrying both clock and data information at different times. Data signals, which may be either encoded or not, are carried through a subset of the bus lines through a mapping scheme that maps the data information to the bus lines at each data transfer while the clock signals are carried in the remaining bus lines. Various mapping schemes are possible.

Abstract: A digital image processor includes an input buffer operable to receive an interlaced video stream and a digital memory for storing portions of the interlaced video stream. An output buffer is operable to transmit a deinterlaced video stream. Also included is a deinterlacing processor coupled between said input buffer and said output buffer and to said digital memory, said deinterlacing processor is operable to store portions of said received interlaced video stream from said input buffer into said digital memory and to detect diagonal features in said portions of said received interlaced video stream in said digital memory, and to generate said deinterlaced video stream having smoothed diagonal features therefrom.

Abstract: In a class of embodiments, an adaptive equalization circuit that implements a joint adaptation algorithm. Other embodiments are receivers that include such an adaptive equalization circuit, and joint adaptation equalization methods. The equalization circuit includes a filter having a low-frequency-gain path (sometimes referred to as a low-frequency filter) and a high-frequency-boosting path (sometimes referred to as a high-frequency filter). The high-frequency filter typically includes a high-pass filter in series with an amplifier having adjustable gain. A high-frequency-boosting tuning loop controls the adjustable gain applied by the high-frequency filter. A low-frequency-gain tuning loop controls the adjustable gain applied by the low-frequency filter.

Abstract: A female edge connector is cut into a circuit board to reduce the connector size and therefore the distance the signal path is separated from the ground plane. Preferably, the female connector is a surface mount connector and is provided in two pieces. This allows the female connector to be attached to either side of the printed circuit board or can be connected to both sides if half of the connector is mounted on the opposite side of the board from the other. A male edge connector of a plug-in board can then be inserted through the aperture formed in the mother board to contact the female edge connector, providing very little distance between the ground planes of the plug-in board and the mother board. The distance between the two pieces of the female connector can be varied by changing the width of the aperture such that PC boards of various thicknesses can be accommodated.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.