Abstract: A method for bi-directional transmission of data between a source and a sink over a two-wire interface includes re-mapping a data signal and a clock signal from a first local bus on the source into a different protocol signal. Transmitting the different protocol signal from the source to the sink over the two-wire interface. Re-mapping the different protocol signal back into the data signal and the clock signal for use on a second local bus on the sink. Re-mapping the data signal and the clock signal from the second local bus into the different protocol signal; and transmitting the different protocol signal from the sink to the source over the two-wire interface.

Abstract: A method for adaptively filtering a control signal in a serial link includes monitoring for a blanking interval in a video stream having an associated clock signal and monitoring for an occurrence of a VSYNC signal once the blanking interval has started. A control signal is initially detected wherein the control signal occurs subsequent to the occurrence of the VSYNC signal. A set of properties of the control signal are recorded and a set of filter parameters are adjusted for detecting the control signal in a next blanking period based on the set of properties of the control signal.

Abstract: A digital image enhancer includes a deinterlacing processor receptive to an interlaced video stream. The deinterlacing processor includes a first deinterlacer and a second deinterlacer and provides a deinterlaced video stream. The digital image enhancer also includes a video output processor receptive to the output of the deinterlaced video stream to provide a scaled, deinterlaced video stream. A portable DVD player including the digital video enhancer has a generally thin prismatic enclosure having a first major surface, a second major surface separated from said first major surface, and side surfaces connecting the first major surface to the second major surface. At least a portion of the first major surface includes a video display, and the enclosure includes a DVD entry port such that a DVD can be inserted into the enclosure.

Abstract: A method of receiving data, in accordance with an embodiment of the present invention, includes the acts of generating a data sampling clock signal and comparing a received clock signal to the data sampling clock signal. The data sampling clock signal is used to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. It is then determined which zone of the sampled data has a transition of the data signal and indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.

Abstract: An apparatus for delaying an audio signal in conformance with the format of the audio signal. An input device is receptive to an audio signal having one of a plurality of formats. A processing device coupled to the input device is operable to provide a delay in the audio signal corresponding to the format of the audio signal. The delayed audio signal is output through an output device. An audio format detection circuit is operable to detect the number of edge transitions within a known period in a processed audio signal and thereby determine the format of the audio signal by comparing a detected edge transition count to model data representative of the plurality of formats.

Abstract: A communication system including two endpoints (transceivers or a transmitter and receiver) and a serial link between them. At least one endpoint is configured to generate encoded data in accordance with a line code and to transmit the encoded data over the link. The line code specifies a block code for encoding cells of application data and control bits, and typically also special characters that do not match bit sequences of encoded cells. Other aspects of the invention are methods for generating (and endpoint devices configured to generate and transmit, or receive and process) such encoded data, and methods for performing functions of multiple layers of a communication protocol in response to such encoded data. In accordance with the invention, multiple levels of communication protocol functionality can be efficiently incorporated within a line code.

Abstract: A system including a multi-port storage device (e.g., a disk drive) and at least two users, each user coupled to a port of the storage device by a serial link. The storage device has an operational portion and an interface (including arbitration circuitry) between its ports and the operational portion. In response to a set of competing priority bids from the users, the arbitration circuitry grants one bid (including by sending an acknowledgement to the successful bidder) and preferably holds each non-granted competing bid without sending any notification to the unsuccessful bidder until the successful bidder sends a deselect signal. The system can be a RAID system including at least two disk drives and at least two controllers, where at least one drive is a multi-port device shared by at least two of the controllers. Preferably, each priority bid and deselect signal is a primitive code (e.g., an ordered sequence of a 10-bit control character and three 10-bit data characters in SATA format).

Abstract: A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

Abstract: Techniques to transmit auxiliary data are disclosed. One technique includes generating a control signal from a video data enable signal and an auxiliary data enable signal, and combining an auxiliary data signal and a video data signal into a composite data signal using the control signal. Techniques to receive the auxiliary data are also disclosed.

Abstract: Apparati, methods, and computer readable media for enabling two parties (1,2) to exchange encrypted messages, exchange symmetric cryptographic keys, and perform functions of public key cryptography. First and second key exchange algorithms use commuting pairs of subsets of a monoid. The first key exchange algorithm has four principal embodiments. In three of the embodiments, a set of matrices over a hyperbolic ring is used as the monoid. In the fourth embodiment, a braid group is used as the monoid. The second key exchange algorithm has five principal embodiments. In four of the embodiments, a set of matrices over a hyperbolic ring is used as the monoid. In the fifth embodiment, a braid group is used as the monoid.

Abstract: A communication system including a transmitter, a receiver, and a serial link (for example, a TMDS-like link) in which video data (or other data) are encrypted, the encrypted data are transmitted from the transmitter to the receiver, and the transmitted data are decrypted in the receiver, a transmitter and a receiver for use in such systems, a cipher engine for use in such a transmitter or receiver, a method for operating such a transmitter or receiver to encrypt or decrypt data, and a method for authenticating a receiver prior to transmission of encrypted data to the receiver over a serial link. Each transmitter, receiver, and cipher engine is configured to implement a content protection protocol in a manner that implements at least one and preferably more than one of a class of attack prevention features disclosed herein.

Abstract: A scheme to reduce clock jitter is disclosed in applications where video content is transmitted through multiple stages, each having a switch allowing that stage's video stream to be selected. The video data is re-clocked using a new clock at each stage. Before re-clocked, the video data from the preceding stage is scaled into a constant resolution using a digital scaler. Since the downstream stages could re-clock the video as if it were sent at the same frequency, there is no need to anticipate the changeable video frequency and to create the necessary low-jitter clock in programmable logic.

Abstract: A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range.

Abstract: A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data, a pixel clock is transmitted over the link, and the receiver regenerates a clock for the audio data using time code data in the packets and the pixel clock. Other aspects of the invention are transmitters for transmitting encoded data and a pixel clock over a serial link, receivers for receiving such data and pixel clock and performing audio clock regeneration, and methods for transmitting encoded data and a pixel clock over a serial link and performing clock regeneration using the transmitted data and pixel clock.

Abstract: A scheme for reducing jitter in high-speed digital communication by adaptively controlling the loop bandwidth of a receiver PLL to reduce the relative jitter between the recovered data and clock. The scheme uses phase pointer activity to represent the relative jitter. The phase pointer activity is measured and used to control the receiver PLL loop bandwidth. The receiver PLL loop bandwidth is repeatedly incremented or decremented by a step size based on the comparison between a newly measured activity value and the old activity value, until the phase pointer activity reaches a minimum. Because the PLL performance requirement of the transmitter can be relaxed, compatibility with legacy transmitters and multi-vendor transmitters is enhanced. Because tight control of fabrication process parameters of PLLs may be relaxed, the fabrication yield may also be improved.

Abstract: A communication system including a transmitter, a receiver, and a serial link, that is capable of transmitting packets of data (e.g., frames of video data) over the link. The transmitter and receiver are operable in any selected one of a transmission mode (in which the data are transmitted over the link from the transmitter to the receiver) and a mute mode in which transmission of data over the link has been interrupted. Typically in the transmission mode, encrypted video data are transmitted and decrypted by the receiver. Other aspects of the invention are transmitters and receivers for use in, and methods implemented by, any embodiment of such system. Typically, each transition between transmission mode and mute mode operation requires that the device undergoing the transition (whether a transmitter or receiver) receives a warning that the transition is to occur.

Abstract: Methods and circuits for measuring clock phase uniformity of multi-phase clock set, including by generating at least one DC phase difference signal such that the DC phase difference signal is, or the DC phase difference signals are, indicative of the phase difference between the clocks of each of multiple pairs of clocks of the clock set, and methods and circuitry for generating such DC phase difference signals. Preferably, multiplexer circuitry asserts to DC signal generation circuitry any selected one of a number of pairs of clocks of the clock set, and the DC signal generation circuitry includes logic (for generating a binary signal in response to each clock pair) and a low pass filter for generating a DC phase difference signal in response to the binary signal. Other aspects are receivers and transmitters that include circuitry for generating at least one DC phase difference signal, and systems including at least one such transmitter (or receiver) and a link (e.g.

Abstract: An interlaced to progressive scan video converter which identifies object edges and directions, and calculates new pixel values based on the edge information. Source image data from a single video field is analyzed to detect object edges and the orientation of those edges. A 2-dimensional array of image elements surrounding each pixel location in the field is high-pass filtered along a number of different rotational vectors, and a null or minimum in the set of filtered data indicates a candidate object edge as well as the direction of that edge. A 2-dimensional array of edge candidates surrounding each pixel location is characterized to invalidate false edges by determining the number of similar and dissimilar edge orientations in the array, and then disqualifying locations which have too many dissimilar or too few similar surrounding edge candidates.

Abstract: In some embodiments, a device detection circuit for detecting whether a device is coupled to a differential link, a transmitter (e.g., a transceiver) including such a circuit, and a system including such a transmitter. Preferably, the device detection circuit includes two branches (each branch including a switch), a current source that causes current to flow through either branch, or to be shared by both branches, depending on the state of each switch, and a voltage swing detector configured to detect the voltage between a node (of one branch) and a node (of the other branch) during a device detection operation. In other embodiments, the invention is a device (e.g., a receiver) including a differential termination that can be coupled to a differential link, and an electrical overstress protection circuit coupled to the termination and configured to protect the device against electrical stress during a hot plug event.

Abstract: A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.