Abstract: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

Abstract: Embodiments of the invention are generally directed to a multi-view display system. An embodiment of an apparatus includes a display screen to display multiple views simultaneously, and a controller to control the views presented on the display screen. The apparatus is configurable by the controller to provide multiple view settings, the view settings including a first setting in which the apparatus provides a single view to each viewer of the display screen and a second setting in which the apparatus provides a first view to a first viewer of the display screen and a second view to a second viewer of the display screen. A first filtering element filters views presented to viewers of the display screen such that an intended view is displayed to one or more viewers.

Abstract: An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface including multiple input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and one or more error recovery modules coupled between the plurality of input ports and output ports, where a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports.

Abstract: A method, apparatus and system are provided for generating and facilitating Mobile High-Definition Multimedia Interface. In one embodiment, an apparatus includes a transmitter configured to merge multiple channels of a high-definition interface into a single channel to generate a mobile high-definition interface, the mobile high-definition interface configured to facilitate carrying of high-definition media content in a mobile device. The apparatus further includes a receiver coupled with the transmitter, the receiver configured to receive the single channel, and to unmerge the single channel into the multiple channels.

Abstract: A technique for reducing noise in a digital video signal is disclosed. In one embodiment, the technique involves receiving a digital signal. The digital signal can be filtered thereby generating a filtered signal. The digital signal and the filtered signal can be mixed according to a composite blend map thereby generating an optimized signal. The optimized signal can be provided as an output.

Abstract: A method and apparatus for group power management of network devices. Some embodiments of an apparatus include a power management module, where the power management module is to transition the apparatus from a normal state to a low power state. The apparatus includes a wake module having a processor that remains active in the low power state, and a register to store a group address. The apparatus includes a network interface that is monitored by the processor in the low power state, where the processor detects a data packet identifying the group address at the network interface, and where the power management module returns the apparatus to the normal state upon detection of the data packet.

Abstract: An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (?), and a second branch including a high pass filter (HPF) and having another variable gain (?). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology so that the gain parameters ? and ? are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. Typically, the inventive equalizer is embodied in a receiver for use in equalizing a signal, indicative of video or other data, that has propagated over a serial link to the receiver.

Abstract: A technique for deinterlacing an interlaced video stream is disclosed. A embodiment of a method includes calculating a pixel using edge detection, calculating a pixel using vertical interpolation, calculating a pixel using weaving, calculating a confidence level, calculating a motion value, blending the edge pixel calculation with the vertical interpolation calculation to generate a first output pixel calculation, the blending being based on the confidence level, and blending the first output pixel calculation with the weaving calculation to generate a second output pixel calculation, the blending being based on the motion value.

Abstract: A method, apparatus and system for employing an automatic data aligner for multiple serial receivers in serial link technologies is provided. In one embodiment, converting a transmission data path of a single bit into a parallel bit via a data aligner, wherein the data is being transmitted via one or more ports. Further, binding data transmission channels to reduce latency in transmission of the data, wherein the binding of the data transmission channels further includes inserting delay to match latency via the one or more ports.

Abstract: Embodiments of the invention are generally directed to fault testing for interconnections. An embodiment of a fault analysis apparatus includes a test pattern source to provide a test pattern for an interconnection between a transmitter and a receiver, the interconnection having a transmitter end and a receiver end, the interconnection including a first wire and a second wire, the transmitter transmitting the test pattern on the first wire to the receiver. The apparatus further includes a first switch to open and close a first connection for the first wire, and a second switch to open and close a second connection for the second wire. The first switch and the second switch are to be set according to a configuration to set at least a portion of a test path for the detection of one or more faults in the interconnection.

Abstract: An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface including multiple input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and one or more error recovery modules coupled between the plurality of input ports and output ports, where a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports.

Abstract: A technique for detecting original scan lines is disclosed. The technique involves receiving a deinterlaced signal with even scan lines and odd scan lines. After the deinterlaced signal is received, a determination is made as to whether the even scan lines or the odd scan lines are the original scan lines. In certain embodiments, an interlaced signal can be generated from the original scan lines. In other embodiments, an optimized deinterlaced signal can be generated using the original scan lines.

Abstract: A method and system for sharing banks of memory in a multi-port memory device between components is provided. The multi-port memory device includes multiple ports to which components of a system are attached, and multiple banks of memory within the multi-port memory device that are shared by each of the ports. A bank availability pin is added to each port for each bank of memory. The bank availability pin is signaled when the bank is available to a particular port and unsignaled when the bank is unavailable. Thus, the multi-port memory device can be shared by several components simultaneously with only a small amount of additional hardware to support the sharing. Also provided are methods for refreshing the banks of memory.

Abstract: Embodiments of the invention are generally directed to determination of physical connectivity status of devices based on electrical measurement. An embodiment of a method includes discovering a connection of a first device with a second device, and performing an electrical measurement of the second device by the first device via the connection between the first device and the second device, where performing the electrical measurement includes sensing by the first device of an element of the second device. The method further includes, if the sensing by the first device fails to detect the element of the second device and a predetermined condition for the electrical measurement is enabled, then determining by the first device that the connection with the second device has been lost.

Abstract: A data sampling circuit that employs an oversampling clock to oversample a data signal, a phase tracking circuit for use in such a sampling circuit, and a receiver and system including such a sampling circuit. Preferably, phase tracking is implemented by systematically identifying and rejecting at least one worst sampling position, and sampling the data signal at a non-rejected sampling position. Preferably, phase tracking is accomplished by counting through-transitions of edges of the sampled data signal through each oversampling position, and rejecting an oversampling position having a highest count of through-transitions. In some embodiments, different phase tracking methods (at least one of which includes the step of generating through-transition counts) are used for different types of input data. Other aspects of the invention are methods for determining an oversampling position for oversampling a data signal, and methods for oversampling a data signal including by generating through-transition counts.

Abstract: Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.

Abstract: A technique for deinterlacing an interlaced video stream is disclosed. A method according to the technique can involve calculating a gradient of image intensity and identifying an edge. A bin can be selected that encompasses the edge. An unknown pixel can be calculated by blending known pixel values along the bin boundaries.

Abstract: Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency.

Abstract: A method, apparatus and system are provided for enhancing port multipliers. In one embodiment, a port multiplier is configured to couple a network host with port multipliers. The port multiplier includes a top port multiplier to establish and maintain communication with each of the port multipliers to communicate with the network host, and the port multipliers having intermediate port multipliers and/or bottom port multipliers. Further, network devices are in communication with the port multipliers, the port multiplier, and the network host.

Abstract: A method, apparatus and system employing a 17B/20B coder is disclosed. The 17B/20B coder to receive an incoming stream including a 17B block and a 20B block, and partition the 17B block into first blocks, and partitioning the 20B into second blocks. The coder is further to code 17B to 20B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17B block and the second blocks of the 20B block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.