Abstract: A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.

Abstract: Techniques to transmit auxiliary data are disclosed. One technique includes generating a control signal from a video data enable signal and an auxiliary data enable signal, and combining an auxiliary data signal and a video data signal into a composite data signal using the control signal. Techniques to receive the auxiliary data are also disclosed.

Abstract: A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and a folded starved inverter circuit contained within the voltage controlled oscillator wherein the folded starved inverter provides two current paths. The dual current paths allow for simultaneous coarse and fine phase tracking. With this low jitter performance and wide operating range, the quad transceiver may be implemented in 0.18-?m CMOS technology, and shows 10?12 bit error rate up to speeds of 3 Gbps.

Abstract: A method and system for sharing banks of memory in a multi-port memory device between components is provided. The multi-port memory device includes multiple ports to which components of a system are attached, and multiple banks of memory within the multi-port memory device that are shared by each of the ports. A bank availability pin is added to each port for each bank of memory. The bank availability pin is signaled when the bank is available to a particular port and unsignaled when the bank is unavailable. Thus, the multi-port memory device can be shared by several components simultaneously with only a small amount of additional hardware to support the sharing. Also provided are methods for refreshing the banks of memory.

Abstract: An integrated circuit that includes operational circuitry and message digest generation circuitry coupled to the operational circuitry, a method for testing an integrated circuit including message digest generation circuitry, and a system including an integrated circuit (which includes message digest generation circuitry) and at least one external device coupled to the integrated circuit. The message digest generation circuitry is coupled and configured to generate at least one digest of at least one message, where each message is indicative of at least one aspect of the integrated circuit's state. For example, a message can be a sequence of voltages or logic levels sampled at a specific sequence of nodes of operational circuitry of the integrated circuit.

Abstract: A data recovery system for a serial digital data link includes a data sampler, compare logic, a phase controller, and a phase shifter. The data sampler samples input data three times in a bit time which time is determined by clock pulses generated by the phase shifter, and recovers digital data according to a predetermined decision criterion. The compare logic compares the output of the data sampler according to a predetermined method. Phase controller uses the output of the compare logic and generates phase control signals. The phase shifter uses the phase control signals and makes three different phase clocks from input clock. The input clock can be an external clock, or can be recovered from the external clock or input data stream.

Abstract: A method and system for switching data in a data switch. In one embodiment, the present invention comprises receiving a plurality of cells at a merged input queue of the data switch, wherein a cell of the plurality of cells is characterized by a priority and a destination. In one embodiment, the destination identifies an output port of the data switch. An age tag is assigned to at least one cell of the plurality of cells. In one embodiment, the age tag indicates the relative length of time a cell of has been in the merged input queue as compared to other cells of the plurality of cells. A portion of the plurality of cells is selected according to a priority selection. It is determined whether any cells of the portion have the same destination. At least one connection request associated with cells of the portion is transmitted, wherein cells having the same destination are transmitted according to the age tag.

Abstract: A preference programmable first-one detector and quadrature based random grant generator in a crossbar switch is disclosed. The crossbar switch emulates a FIFO switching function in a single chip crossbar switch architecture that operates at a high switching speed with a large bandwidth and supports multiple QoS levels, yet do not demand an inordinately large number of input and output queues or otherwise excessively tax memory requirements. The system and method operate at a high switching speed with a large bandwidth and support multiple QoS levels, yet do not require a complex pointer management system, nor constrain switching speeds and bandwidth capacity therein. The system and method efficiently select data for switching within a crossbar switch based structure based on an urgency counter based WRR grant selection. This switching is achieved with economy of hardware by quadrature basing and quadrature preference selection.

Abstract: In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal.

Abstract: In a class of embodiments, the invention is an open computing system (e.g., a PC) in which a protected, closed subsystem is embedded. The closed subsystem typically includes multiple parts that ensure that content protection keys and protected content are never revealed outside the closed subsystem. Content (e.g., high-definition digital video) that enters the closed subsystem (and is typically decrypted and re-encrypted within the closed subsystem) is afforded a similar level of protection within the open system as can be obtained in standalone closed systems. Other aspects of the invention are methods for protecting content within an open computing system, a closed system (or disk drive thereof) configured to be embedded in an open computing system, and circuitry configured to be embedded in an open computing system for combining the output of a closed subsystem with other output (e.g., graphics and/or audio output) of the open computing system.

Abstract: A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information.

Abstract: A digital image processor is provided. The digital image processor includes a deinterlacing processor that is implemented upon a digital processing unit. The deinterlacing processor is coupled to an input operable to receive an interlaced video stream, a digital memory for storing portions of the interlaced video signal, and an output operable to transmit a deinterlaced video stream. The deinterlacing processor is operable to perform frequency analysis upon the received interlaced video stream in order to generate the deinterlaced video stream having reduced motion artifacts.

Abstract: A method efficiently multicasts data within a crossbar switch based structure. Multicasting is achieved with effective prioritization of multicast data with respect to unicast data and other multicast data, yet does not unnecessarily delay unicast traffic. The method for multicast service in a crossbar switch effectuates the transfer of data between a single input queue and a multiplicity of output ports and reconfigures the crossbar switch accordingly. A primacy is assigned to data cells based upon their designation as multicast cells that hightens their service priority with respect to cells that are to be unicasted. To prioritize multicast cells for service with respect to other multicast cells, a comparison of assigned priorities is made. While multicast cells have priority in one embodiment over unicast cells, unicast cells can be transferred during multicast iterations during pauses in multicast data transfer.

Abstract: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair.

Abstract: In some embodiments, a chip includes sampling circuitry to produce oversampled data from a received signal, and logic to determine which of the oversampled data are to be part of different unit intervals, wherein some of the unit intervals have a number of oversampled data that is different than a number of oversampled data typically included in the unit intervals. Other embodiments are described and claimed.

Abstract: A method for bi-directional transmission of data between a source and a sink over a two-wire interface includes re-mapping a data signal and a clock signal from a first local bus on the source into a different protocol signal. Transmitting the different protocol signal from the source to the sink over the two-wire interface. Re-mapping the different protocol signal back into the data signal and the clock signal for use on a second local bus on the sink. Re-mapping the data signal and the clock signal from the second local bus into the different protocol signal; and transmitting the different protocol signal from the sink to the source over the two-wire interface.

Abstract: A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but provides a power-saving mode for transferring data while consuming less power. In the normal mode, the hybrid clock system contains a reference clock that operates at a low frequency that drives a PLL. The PLL multiplies the reference clock frequency to a much higher frequency, and supplies the clock signal to a data transfer circuit. In the power-saving mode, the hybrid clock system turns off the PLL and connects the reference clock directly to the data transfer circuit.

Abstract: In preferred embodiments, a cryptographic device in which two key sets are stored: a normal key set (typically unique to the device) and a test key set (typically used by each of a relatively large number of devices). The device uses the normal key set in a normal operating mode and uses the test key set in at least one test mode which can be a built-in self test mode. Alternatively, the device stores test data (e.g., an intermediate result of an authentication exchange) in addition to or instead of the test key set. In other embodiments, the invention is a cryptographic device including a cache memory which caches a portion of a key set for performing an authentication exchange and/or at least one authentication value generated during an authentication exchange. Other embodiments of the invention are systems including devices that embody the invention and methods that can be performed by systems or devices that embody the invention.

Abstract: A method for removing MPEG-2 chroma upconversion artifacts in a video stream includes detecting a presence of artifacts in an incorrectly upsampled MPEG-2 video stream and removing the presence of artifacts resulting in an artifact free video stream.

Abstract: A method and apparatus for 2× oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 ?m CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10?12.