Abstract: Embodiments of the invention are generally directed to de-encapsulation of data streams into multiple links. An embodiment of a method includes receiving a data stream including multiple data frames, the data stream being in a first mode having a multiple channels of content data including a first channel sent in a first position in each data frame and a second channel sent in a second position in each data frame following the first position, with each data frame including a synchronization signal to indicate a start of the content data. The method further includes transforming the data stream into data sub-streams in a second mode, the data sub-streams including a first data sub-stream to carry data for the first channel in the second mode and a second data sub-stream to carry data for the second channel in the second mode.

Abstract: Embodiments of the invention are generally directed to transmission and handling of three-dimensional video content. An embodiment of a method includes receiving a multimedia data stream including video data utilizing an interface protocol and determining that the received video data includes three-dimensional (3D) video data, where each frame of the video data includes a first vertical synchronization (Vsync) signal prior to an active data region, the active data region including a first data region and a second data region. The method further includes converting the 3D video data from a 3D data format to a two-dimensional (2D) video format, where converting the 3D video data includes identifying a region between the first data region and the second data region, inserting a second Vsync signal between the first data region and the second data region, and providing an identifier to distinguish between the first data region and the second data region.

Abstract: A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.

Abstract: An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“ICs”) includes an N-bit-to-N+2-bit (“N bit/(N+2) bit”) physical layer (“PHY”) encoder configured to insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and encode said N+1 unencoded data bits to yield N+2 encoded data bits. The apparatus further includes an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit, wherein N represents any integer number of data bits.

Abstract: A method and apparatus for synchronizing related data streams in interconnection networks. Some embodiments of an apparatus include a transmitter to transmit a data stream to a second apparatus, where the transmitter transmits a data packet to the second apparatus. The apparatus further includes a clock, with the apparatus providing a first timestamp for the data packet using the clock upon transmission of the data packet. The apparatus includes a receiver to receive responses from the second apparatus, with the apparatus providing a second timestamp upon receiving a returned packet from the second apparatus, with the returned packet containing timestamps for the receipt and transmission of the packet by the second apparatus. The apparatus includes a network unit to direct the operation of the apparatus, the network unit to determine a start time for decoding of the data stream by the second apparatus based at least in part on the timestamps for the packet.

Abstract: Discovery of electronic devices utilizing a control bus. An embodiment of a method includes connecting a receiving device to a cable, where the cable includes a control bus. If the receiving device is in a disconnect state and a signal from a transmitting device is detected on the control bus, the device is transferred to a state for a first type of transmitting device. If the receiving device is in either the disconnect state or the state for the first type of transmitting device and a predetermined voltage signal is received from the transmitting device, then the receiving device is transferred to a state for a second type of transmitting device.

Abstract: A method and apparatus for packet level prioritization in interconnection networks. An embodiment of an apparatus includes a transmitter to transmit a data stream to a recipient apparatus, the data stream including a plurality of data packets, the data packets including data packets of a first priority and data packets of a second priority. The apparatus further includes a network unit to direct the operation of the transmitter, the network unit to divide the data stream into multiple sub-streams, including a first sub-stream for data packets of the first priority and a second sub-stream for data packets of the second priority.

Abstract: A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced.

Abstract: A method, apparatus and system for employing an enhanced port multiplier are provided. In one embodiment, a network host is configured to be coupled with a port multiplier in a network. The port multiplier is configured into being cascaded into being coupled with a plurality of port multipliers and a plurality of network devices.

Abstract: A method and apparatus for bandwidth reservation for data flows in interconnection networks. Some embodiments of an apparatus for transmitting a data stream include a transmitter to transmit a data stream to a recipient apparatus, the data stream including a plurality of data packets. The apparatus further includes a receiver to receive a response from the recipient apparatus regarding data packet arrival status, and a network unit to direct the operation of the transmitter, the network unit to direct the transmitter to maintain the data stream with a constant bandwidth.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A communication system including a transmitter, a receiver, and a serial link (for example, a TMDS-like link) in which video data (or other data) are encrypted, the encrypted data are transmitted from the transmitter to the receiver, and the transmitted data are decrypted in the receiver, a transmitter and a receiver for use in such systems, a cipher engine for use in such a transmitter or receiver, a method for operating such a transmitter or receiver to encrypt or decrypt data, and a method for authenticating a receiver prior to transmission of encrypted data to the receiver over a serial link. Each transmitter, receiver, and cipher engine is configured to implement a content protection protocol in a manner that implements at least one and preferably more than one of a class of attack prevention features disclosed herein.

Abstract: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

Abstract: A method and apparatus for a control bus for connection of electronic devices. An embodiment of a method includes coupling a transmitting device to a receiving device, including connecting a control bus between the transmitting device and the receiving device, with the control bus being a bi-directional, single-line bus. The method further includes obtaining control of the control bus for either the transmitting device or the receiving device, with the device obtaining control becoming an initiator and the other device becoming a follower. One or more control signals are converted to one or more data packets, with each of the one or more control signals representing one of multiple different types of control signals. The generated data packets are transmitted from the initiator to the follower via the control bus.

Abstract: A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but provides a power-saving mode for transferring data while consuming less power. In the normal mode, the hybrid clock system contains a reference clock that operates at a low frequency that drives a PLL. The PLL multiplies the reference clock frequency to a much higher frequency, and supplies the clock signal to a data transfer circuit. In the power-saving mode, the hybrid clock system turns off the PLL and connects the reference clock directly to the data transfer circuit.

Abstract: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair.

Abstract: In some embodiments, a device includes a bus, a parallel source, and a parallel sink. The parallel source is to provide parallel groups of signals including video signals to the bus, wherein the bus has a number of lanes that is fewer than a number of signals used to represent a pixel such that pixels are represented in more than one of the parallel groups. The parallel sink is to receive the parallel groups of signals from the bus, wherein the parallel sink includes a signal extractor to separate at least a portion of the groups of signals into multiple channels, and encoder and serializer circuits to encode and serialize the separated signals. Other embodiments are described and claimed.

Abstract: Methods and computer readable media for performing scan-based testing of circuits using one or more test clock control structures are disclosed. In one embodiment, a method includes performing an intra-domain test to exercise a first subset of domains of the plurality of circuits implementing dynamic fault detection test patterns. It also includes performing an inter-domain test to exercise a second subset of domains of the plurality of circuits implementing dynamic fault detection test patterns. The dynamic fault detection test patterns can include, for example, last-shift-launch test patterns and broadside test patterns. In various embodiments, the method can include configuring different programmable test clock controllers to test different domains substantially in parallel.

Abstract: Embodiments of the invention are generally directed to operation of a media interface to provide bidirectional communications. An embodiment of a method includes connecting a first device to a second device via a media interface, the media interface including a communication channels for unidirectional data transmission, the media interface being in compliance with a media protocol. The method further provides for configuring the first device and the second device for bidirectional data transmission, the bidirectional data transmission being conducted according to a network protocol, and transmitting bidirectional data between the first device and the second device via the media interface.

Abstract: In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal. Other embodiments are described and claimed.