Abstract: A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.

Abstract: In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal. Other embodiments are described and claimed.

Abstract: In preferred embodiments, a cryptographic device in which two key sets are stored: a normal key set (typically unique to the device) and a test key set (typically used by each of a relatively large number of devices). The device uses the normal key set in a normal operating mode and uses the test key set in at least one test mode which can be a built-in self test mode. Alternatively, the device stores test data (e.g., an intermediate result of an authentication exchange) in addition to or instead of the test key set. In other embodiments, the invention is a cryptographic device including a cache memory which caches a portion of a key set for performing an authentication exchange and/or at least one authentication value generated during an authentication exchange. Other embodiments of the invention are systems including devices that embody the invention and methods that can be performed by systems or devices that embody the invention.

Abstract: Systems, structures and methods for generating a test clock for scan chains to implement scan-based testing of electronic circuits are disclosed. In one embodiment, a test clock control structure includes a programmable test clock controller. The programmable test clock controller includes a test clock generator for generating a configurable test clock. It also includes a scan layer interface to drive a scan chain portion with the configurable test clock, and a control layer interface configured to access control information for controlling the scan chain portion. In another embodiment, a method effectuates scan-based testing of circuits. The method includes performing at least one intra-domain test and performing at least one inter-domain test using implementing dynamic fault detection test patterns, which can include last-shift-launch test patterns and broadside test patterns.

Abstract: A method and apparatus for parameter scanning for signal over-sampling. An embodiment of an apparatus includes an equalizer to equalize received data values, and a sampler to over-sample the equalized data. The apparatus includes an eye monitor to generate information regarding quality of signal eyes for the over-sampled data, and an equalization monitor to generate information regarding sufficiency of signal equalization. The apparatus further includes a scan engine to scan possible values of a plurality of parameters for the apparatus.

Abstract: A method, apparatus and system employing a coder is disclosed. The coder to receive an incoming stream including a first code block and a second code block, and partition the first code block into first small code blocks, and partition the second code block into second small code blocks. The coder is further to code a memory that uses one or more serial lines for communication is performed, wherein coding includes coding the first small code blocks of the first code block and the second small code blocks of the second code block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.

Abstract: A system for implementing a content protection protocol to encrypt data, including transmitters and receivers to which key selection vectors of a vector set have been distributed, wherein a subset of the key selection vectors in the vector set has not been distributed to any of the transmitters or any of the receivers, and a method for enabling transmitters and receivers to implement a content protection protocol including by distributing key selection vectors of a vector set, and private key sets, to the transmitters and receivers while reserving a subset of the key selection vectors of the vector set.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

Abstract: In some embodiments, the invention is a personal digital network (“PDN”) including hardware (sometimes referred to as Ingress circuitry) configured to transcrypt encrypted content that enters the PDN. Typically, the transcryption (decryption followed by re-encryption) is performed in hardware within the Ingress circuitry and the re-encryption occurs before the decrypted content is accessible by hardware or software external to the Ingress circuitry. Typically, transcrypted content that leaves the Ingress circuitry remains in re-encrypted form within the PDN whenever it is transferred between integrated circuits or is otherwise easily accessible by software, until it is decrypted within hardware (sometimes referred to as Egress circuitry) for display or playback or output from the PDN.

Abstract: In some embodiments, an apparatus includes conductors, and a transmitter including transmitter test circuitry to embed test properties in test pattern signals, and transmit the test pattern signals to the conductors. In some embodiments, an apparatus includes conductors to carry test pattern signals with embedded test properties, and receiver test circuitry to receive the test pattern signals and extract the test properties and determine whether the extracted test properties match expected test properties. Other embodiments are described and claimed.

Abstract: An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode a subset of encoded data bits to yield decoded data bits. It also includes a physical interface (“PI”) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits. As such, the apparatus uses the physical interface error detection bit to determine whether the encoded data bits include at least one erroneous data bit as an error. In some embodiments, the apparatus includes an error detector configured to operate within a physical layer. In at least one embodiment, the apparatus efficiently transmits error detection codes within, for example, an NB/(N+1)B line coder.

Abstract: A multi-port memory device having two or more ports wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock and a port clock. The system clock is applied to port logic that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.

Abstract: An interlace motion artifact detector which identifies video image spatial frequencies characteristic of motion artifacts. The detected frequency is the maximum which can be represented by the vertical sampling rate of the video format (i.e., the Nyquist frequency). This frequency is detected by a pair of partial Discrete Fourier Transforms (DFT) which each calculate only the frequency component of interest. Additional vertical frequency components at one half and one quarter the interlace motion artifact frequency are also detected via a partial DFT. The presence of these lower frequencies acts as an indication of an erroneous motion artifact detection. Additionally, the dynamic range and maximum level of the video data is used as an indication of when to boost the frequency detection levels in areas of low brightness and/or contrast.

Abstract: A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.

Abstract: A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N?K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.

Abstract: In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.

Abstract: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

Abstract: A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N?K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.

Abstract: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.