Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A communication system including a transmitter, a receiver, a communication link (for example, a TMDS-like link), and preferably also an external agent with which the transmitter and receiver can communicate, in which video data (or other data) are encrypted, the encrypted data are transmitted from the transmitter to the receiver, and the transmitted data are decrypted in the receiver, a transmitter and a receiver for use in such a system, a cipher engine for use in such a transmitter or receiver, a method for operating such a transmitter or receiver to encrypt or decrypt data, and a method for distributing keys to the transmitter and receiver. The receiver can be a player coupled to a downstream receiver by a TMDS-like link, and configured to re-encrypt the decrypted data (for example, using an AES or HDCP protocol) and send re-encrypted data over the link to the receiver.

Abstract: A data sampling method and circuit employing an oversampling clock to oversample a data signal, a phase tracker for use with or in a data sampling circuit, and a method for identifying a sequence of best sampling positions for sampling a data signal from signal samples generated using an oversampling clock. In some embodiments, data indicative of the phase of at least one of the oversampling clock's sampling positions relative to the center of the data eye are low-pass filtered in a manner determined by the data signal's bit rate. In other embodiments, the number of dead cycles of the phase tracker decision loop is reduced by generating possible solutions in parallel and moving the feedback point so as to occur as late as practical, or the phase tracker ignores a sample set when updating its determination of the best sampling position when the sample set indicates that the data signal has less than a predetermined number of transitions during a corresponding tracking period.

Abstract: Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.

Abstract: A method for bi-directional transmission of data between a source and a sink over a two-wire interface includes re-mapping a data signal and a clock signal from a first local bus on the source into a different protocol signal. Transmitting the different protocol signal from the source to the sink over the two-wire interface. Re-mapping the different protocol signal back into the data signal and the clock signal for use on a second local bus on the sink. Re-mapping the data signal and the clock signal from the second local bus into the different protocol signal; and transmitting the different protocol signal from the sink to the source over the two-wire interface.

Abstract: A method for adaptively filtering a control signal in a serial link includes monitoring for a blanking interval in a video stream having an associated clock signal and monitoring for an occurrence of a VSYNC signal once the blanking interval has started. A control signal is initially detected wherein the control signal occurs subsequent to the occurrence of the VSYNC signal. A set of properties of the control signal are recorded and a set of filter parameters are adjusted for detecting the control signal in a next blanking period based on the set of properties of the control signal.

Abstract: A digital image enhancer includes a deinterlacing processor receptive to an interlaced video stream. The deinterlacing processor includes a first deinterlacer and a second deinterlacer and provides a deinterlaced video stream. The digital image enhancer also includes a video output processor receptive to the output of the deinterlaced video stream to provide a scaled, deinterlaced video stream. A portable DVD player including the digital video enhancer has a generally thin prismatic enclosure having a first major surface, a second major surface separated from said first major surface, and side surfaces connecting the first major surface to the second major surface. At least a portion of the first major surface includes a video display, and the enclosure includes a DVD entry port such that a DVD can be inserted into the enclosure.

Abstract: A method of receiving data, in accordance with an embodiment of the present invention, includes the acts of generating a data sampling clock signal and comparing a received clock signal to the data sampling clock signal. The data sampling clock signal is used to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. It is then determined which zone of the sampled data has a transition of the data signal and indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.

Abstract: An apparatus for delaying an audio signal in conformance with the format of the audio signal. An input device is receptive to an audio signal having one of a plurality of formats. A processing device coupled to the input device is operable to provide a delay in the audio signal corresponding to the format of the audio signal. The delayed audio signal is output through an output device. An audio format detection circuit is operable to detect the number of edge transitions within a known period in a processed audio signal and thereby determine the format of the audio signal by comparing a detected edge transition count to model data representative of the plurality of formats.

Abstract: A communication system including two endpoints (transceivers or a transmitter and receiver) and a serial link between them. At least one endpoint is configured to generate encoded data in accordance with a line code and to transmit the encoded data over the link. The line code specifies a block code for encoding cells of application data and control bits, and typically also special characters that do not match bit sequences of encoded cells. Other aspects of the invention are methods for generating (and endpoint devices configured to generate and transmit, or receive and process) such encoded data, and methods for performing functions of multiple layers of a communication protocol in response to such encoded data. In accordance with the invention, multiple levels of communication protocol functionality can be efficiently incorporated within a line code.

Abstract: A system including a multi-port storage device (e.g., a disk drive) and at least two users, each user coupled to a port of the storage device by a serial link. The storage device has an operational portion and an interface (including arbitration circuitry) between its ports and the operational portion. In response to a set of competing priority bids from the users, the arbitration circuitry grants one bid (including by sending an acknowledgement to the successful bidder) and preferably holds each non-granted competing bid without sending any notification to the unsuccessful bidder until the successful bidder sends a deselect signal. The system can be a RAID system including at least two disk drives and at least two controllers, where at least one drive is a multi-port device shared by at least two of the controllers. Preferably, each priority bid and deselect signal is a primitive code (e.g., an ordered sequence of a 10-bit control character and three 10-bit data characters in SATA format).

Abstract: A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: Techniques to transmit auxiliary data are disclosed. One technique includes generating a control signal from a video data enable signal and an auxiliary data enable signal, and combining an auxiliary data signal and a video data signal into a composite data signal using the control signal. Techniques to receive the auxiliary data are also disclosed.

Abstract: Apparati, methods, and computer readable media for enabling two parties (1,2) to exchange encrypted messages, exchange symmetric cryptographic keys, and perform functions of public key cryptography. First and second key exchange algorithms use commuting pairs of subsets of a monoid. The first key exchange algorithm has four principal embodiments. In three of the embodiments, a set of matrices over a hyperbolic ring is used as the monoid. In the fourth embodiment, a braid group is used as the monoid. The second key exchange algorithm has five principal embodiments. In four of the embodiments, a set of matrices over a hyperbolic ring is used as the monoid. In the fifth embodiment, a braid group is used as the monoid.

Abstract: A communication system including a transmitter, a receiver, and a serial link (for example, a TMDS-like link) in which video data (or other data) are encrypted, the encrypted data are transmitted from the transmitter to the receiver, and the transmitted data are decrypted in the receiver, a transmitter and a receiver for use in such systems, a cipher engine for use in such a transmitter or receiver, a method for operating such a transmitter or receiver to encrypt or decrypt data, and a method for authenticating a receiver prior to transmission of encrypted data to the receiver over a serial link. Each transmitter, receiver, and cipher engine is configured to implement a content protection protocol in a manner that implements at least one and preferably more than one of a class of attack prevention features disclosed herein.

Abstract: A scheme to reduce clock jitter is disclosed in applications where video content is transmitted through multiple stages, each having a switch allowing that stage's video stream to be selected. The video data is re-clocked using a new clock at each stage. Before re-clocked, the video data from the preceding stage is scaled into a constant resolution using a digital scaler. Since the downstream stages could re-clock the video as if it were sent at the same frequency, there is no need to anticipate the changeable video frequency and to create the necessary low-jitter clock in programmable logic.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: In a pixel display there is disclosed a pixel arrangement for LCD displays having 5 subpixel components. Namely, red, blue, green with adjacent red green pixels bordered by blue subpixels. Circuitry is disclosed for such pixels in which capacitors, functioning in sample hold circuits receive pulses to their terminal immediately after transistors are open with the resulting voltage change there occurring as an unintended voltage signal being applied to an LCD cell thereby causing unintended image artifacts. A new circuit and method is disclosed by which no transistor is open without its sample and hold stable for the remainder of the frame. Thus, preceding gate lines are tied through subsequent transistors such that all transistors open after the capacitors have their reference terminal stablized. In this way, leakage current does not occur through the source and drain of the transistors attended and certain subpixels do not have unintended image artifacts present.

Abstract: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.