Abstract: A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range.

Abstract: A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data, a pixel clock is transmitted over the link, and the receiver regenerates a clock for the audio data using time code data in the packets and the pixel clock. Other aspects of the invention are transmitters for transmitting encoded data and a pixel clock over a serial link, receivers for receiving such data and pixel clock and performing audio clock regeneration, and methods for transmitting encoded data and a pixel clock over a serial link and performing clock regeneration using the transmitted data and pixel clock.

Abstract: A scheme for reducing jitter in high-speed digital communication by adaptively controlling the loop bandwidth of a receiver PLL to reduce the relative jitter between the recovered data and clock. The scheme uses phase pointer activity to represent the relative jitter. The phase pointer activity is measured and used to control the receiver PLL loop bandwidth. The receiver PLL loop bandwidth is repeatedly incremented or decremented by a step size based on the comparison between a newly measured activity value and the old activity value, until the phase pointer activity reaches a minimum. Because the PLL performance requirement of the transmitter can be relaxed, compatibility with legacy transmitters and multi-vendor transmitters is enhanced. Because tight control of fabrication process parameters of PLLs may be relaxed, the fabrication yield may also be improved.

Abstract: Logic gates are provided that include a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) to produce a gate threshold voltage that differs from a mid-supply voltage level, while providing symmetry in the switching transients of the output logic signals. In one embodiment, the logic gate is a NAND gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level. In another embodiment, the logic gate is a NOR gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A communication system including a transmitter, a receiver, and a serial link, that is capable of transmitting packets of data (e.g., frames of video data) over the link. The transmitter and receiver are operable in any selected one of a transmission mode (in which the data are transmitted over the link from the transmitter to the receiver) and a mute mode in which transmission of data over the link has been interrupted. Typically in the transmission mode, encrypted video data are transmitted and decrypted by the receiver. Other aspects of the invention are transmitters and receivers for use in, and methods implemented by, any embodiment of such system. Typically, each transition between transmission mode and mute mode operation requires that the device undergoing the transition (whether a transmitter or receiver) receives a warning that the transition is to occur.

Abstract: Methods and circuits for measuring clock phase uniformity of multi-phase clock set, including by generating at least one DC phase difference signal such that the DC phase difference signal is, or the DC phase difference signals are, indicative of the phase difference between the clocks of each of multiple pairs of clocks of the clock set, and methods and circuitry for generating such DC phase difference signals. Preferably, multiplexer circuitry asserts to DC signal generation circuitry any selected one of a number of pairs of clocks of the clock set, and the DC signal generation circuitry includes logic (for generating a binary signal in response to each clock pair) and a low pass filter for generating a DC phase difference signal in response to the binary signal. Other aspects are receivers and transmitters that include circuitry for generating at least one DC phase difference signal, and systems including at least one such transmitter (or receiver) and a link (e.g.

Abstract: A digital image processor is provided. The digital image processor includes a deinterlacing processor that is implemented upon a digital processing unit. The deinterlacing processor is coupled to an input operable to receive an interlaced video stream, a digital memory for storing portions of the interlaced video signal, and an output operable to transmit a deinterlaced video stream. The deinterlacing processor is operable to perform frequency analysis upon the received interlaced video stream in order to generate the deinterlaced video stream having reduced motion artifacts.

Abstract: An interlaced to progressive scan video converter which identifies object edges and directions, and calculates new pixel values based on the edge information. Source image data from a single video field is analyzed to detect object edges and the orientation of those edges. A 2-dimensional array of image elements surrounding each pixel location in the field is high-pass filtered along a number of different rotational vectors, and a null or minimum in the set of filtered data indicates a candidate object edge as well as the direction of that edge. A 2-dimensional array of edge candidates surrounding each pixel location is characterized to invalidate false edges by determining the number of similar and dissimilar edge orientations in the array, and then disqualifying locations which have too many dissimilar or too few similar surrounding edge candidates.

Abstract: In some embodiments, a device detection circuit for detecting whether a device is coupled to a differential link, a transmitter (e.g., a transceiver) including such a circuit, and a system including such a transmitter. Preferably, the device detection circuit includes two branches (each branch including a switch), a current source that causes current to flow through either branch, or to be shared by both branches, depending on the state of each switch, and a voltage swing detector configured to detect the voltage between a node (of one branch) and a node (of the other branch) during a device detection operation. In other embodiments, the invention is a device (e.g., a receiver) including a differential termination that can be coupled to a differential link, and an electrical overstress protection circuit coupled to the termination and configured to protect the device against electrical stress during a hot plug event.

Abstract: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture can provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture can also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.

Abstract: The present invention relates to a serial interface transmission system with more than one data line, in which the transmitted data has in-band and out-of-band characters. More particularly, the present invention relates to methods and systems for sending side channel data over a high-speed digital communications link, e.g., a video link. One embodiment of the invention provides a high-speed digital transmitter capable of sending side channel data. The transmitter includes a channel zero encoder, a multiplexer, data enable out (DEout) control logic, and a channel one encoder. The channel one encoder receives input from the channel one multiplexer and the channel one DEout control logic. Another embodiment of the invention provides a high-speed digital receiver capable of receiving side channel data. The receiver includes a channel zero decoder, a channel one decoder, DEI signal and FIFO control signal recovery logic, and a channel one de-multiplexer.

Abstract: A system and method for measuring and utilizing a pseudo pixel error rate in digital data transmission is disclosed. As an alternative to measuring actual pixel error rate measurement, the present invention uses a pseudo pixel error rate detection scheme where the errors occurred in the special character patterns used in data encoding are measured. A particular embodiment uses a de-glitch filter for filtering the glitches from an unfiltered data enable (DE), a delay for delaying the unfiltered DE to match the delay of the de-glitch filter, and a comparator for comparing the unfiltered DE and the filtered DE to determine the occurrence of an error. It further includes a counter to count the errors occurred.

Abstract: A display module driving system wherein digital pixel data for an image to be displayed is provided to a plurality of column drivers on a row by row basis in serial format over a plurality of dedicated bus lines rather than a single parallel bus line. Digital pixel data for a complete image row is divided into segments, wherein the number of segments is each to the number of column drivers. Each segments is then serialized and transmitted to a corresponding column driver such that the digital pixel data for an entire row is transferred to each of the plurality of column drivers at the same time. The column drivers receive the segments and rearrange the data into parallel. The pixels are then transferred to a digital to analog converter, preferably two pixels at a time, where each pixel is converted into analog red, green and blue signals.

Abstract: A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively.

Abstract: A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link.

Abstract: An interlace motion artifact detector which identifies video image spatial frequencies characteristic of motion artifacts. The detected frequency is the maximum which can be represented by the vertical sampling rate of the video format (i.e., the Nyquist frequency). This frequency is detected by a pair of partial Discrete Fourier Transforms (DFT) which each calculate only the frequency component of interest. Additional vertical frequency components at one half and one quarter the interlace motion artifact frequency are also detected via a partial DFT. The presence of these lower frequencies acts as an indication of an erroneous motion artifact detection. Additionally, the dynamic range and maximum level of the video data is used as an indication of when to boost the frequency detection levels in areas of low brightness and/or contrast.

Abstract: A serial data transmission system in which a transmitter encodes data in accordance with a TMDS-like encoding algorithm and transmits the TMDS-like encoded data over a serial link to a receiver. The encoded data are transmitted as a run length limited (“RLL”) code word sequence, including transition-minimized code words. In some embodiments, the RLL code word sequence includes only Min words, including both DC balancing Min words and DC unbalancing Min words. In other embodiments, the RLL code word sequence includes both transition-maximized code words and transition-minimized code words. Other aspects of the invention are circuitry and methods for TMDS-like encoding of data for transmission as an RLL code word sequence.