Abstract: A system and a method for simple and robust baud-rate timing recovery suitable for jointly operating with a decision-feedback equalizer are disclosed. Timing functions for timing recovery are extracted only from filter coefficients of feed-forward and feedback filters. The relation between the coefficients of feed-forward filter and the impulse response is derived under a zero-forcing condition while the relation between the coefficients of the feedback filter and the impulse response is known. Based on the relations, several timing functions with varied degrees of computation are derived, which can drive the sampling instances approximately at the peak point of the channel impulse response. Since the derived timing functions use equalizer coefficients, they work jointly with equalization even without using a training sequence. Simulation results over 5-m and 100-m UTP Category-5 cables at 125M Baud show fast and robust timing recovery operation in a phase-locked loop.

Abstract: A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

Abstract: A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

Abstract: The invention relates to computer graphics and computer imaging on a video display, and includes the dynamic detection of video windows and graphical images overlapping one another. A display processor identifies differences between typical video and graphics data sources to detect the edges of video windows. By detecting the edges of active video windows within a graphics image, a display processor may uniquely adjust image characteristics of an exposed video window. These characteristics include, for example, hue, brightness, intensity and contrast.

Abstract: The present invention is directed to systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of: a) performing transition controlled encoding of a first sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to produce masked n+1 bit data characters; c) DC balancing the masked n+1 bit data characters to produce DC balanced, masked n+2 bit data characters; d) scrambling the DC balanced, masked n+2 bit data characters using a scrambling formula to produce encrypted n+2 bit data characters; e) encoding control data into encoded n+2 bit control characters, f) generating a serial data stream in response to the encrypted data characters and encoded control characters, and g) transmitting the serial data stream over a communication link.

Abstract: A deinterlacing system which converts an interlaced video stream into a progressive video stream is disclosed. The deinterlacing system includes a field assembly responsive to a last field, a next field, a current field and progressive source phase and operative to develop a progressive output frame, a source detection module responsive to last, next and current fields and operative to develop a progressive source phase and a progressive source detected and an intra-frame deinterlacer responsive to the progressive output frame and the progressive source detected and operative to develop a progressive frame output.

Abstract: A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.

Abstract: A method for connecting to an SATA storage component includes a chassis having an interior and an exterior, and a wall portion provided with an opening. An SATA compatible connector, provided with a first restraining flange and a second restraining flange spaced from the first restraining flange, is inserted into the opening in the wall portion, wherein an interior surface of the first restraining flange faces a first surface of the wall portion and an interior surface of the second restraining flange faces a second surface of the wall portion. An SATA storage component is then inserted into the chassis such that it connects with the SATA compatible connector, whereby the first and second flange allows the SATA compatible connector to float in a limited fashion within the opening.

Abstract: A system and method for embedding at least one clock signal into bus lines that also carry data signals at other times to enable a high-speed bus is disclosed. Each bus line is used for carrying both clock and data information at different times. Data signals, which may be either encoded or not, are carried through a subset of the bus lines through a mapping scheme that maps the data information to the bus lines at each data transfer while the clock signals are carried in the remaining bus lines. Various mapping schemes are possible.

Abstract: A digital image processor includes an input buffer operable to receive an interlaced video stream and a digital memory for storing portions of the interlaced video stream. An output buffer is operable to transmit a deinterlaced video stream. Also included is a deinterlacing processor coupled between said input buffer and said output buffer and to said digital memory, said deinterlacing processor is operable to store portions of said received interlaced video stream from said input buffer into said digital memory and to detect diagonal features in said portions of said received interlaced video stream in said digital memory, and to generate said deinterlaced video stream having smoothed diagonal features therefrom.

Abstract: In a class of embodiments, an adaptive equalization circuit that implements a joint adaptation algorithm. Other embodiments are receivers that include such an adaptive equalization circuit, and joint adaptation equalization methods. The equalization circuit includes a filter having a low-frequency-gain path (sometimes referred to as a low-frequency filter) and a high-frequency-boosting path (sometimes referred to as a high-frequency filter). The high-frequency filter typically includes a high-pass filter in series with an amplifier having adjustable gain. A high-frequency-boosting tuning loop controls the adjustable gain applied by the high-frequency filter. A low-frequency-gain tuning loop controls the adjustable gain applied by the low-frequency filter.

Abstract: A female edge connector is cut into a circuit board to reduce the connector size and therefore the distance the signal path is separated from the ground plane. Preferably, the female connector is a surface mount connector and is provided in two pieces. This allows the female connector to be attached to either side of the printed circuit board or can be connected to both sides if half of the connector is mounted on the opposite side of the board from the other. A male edge connector of a plug-in board can then be inserted through the aperture formed in the mother board to contact the female edge connector, providing very little distance between the ground planes of the plug-in board and the mother board. The distance between the two pieces of the female connector can be varied by changing the width of the aperture such that PC boards of various thicknesses can be accommodated.

Abstract: A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (“VCO”) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e.g., a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A method and apparatus for encoding or decoding data in accordance with an NB/(N+1)B block code, and a method for determining codebooks for use in such encoding or decoding. Some such methods select positive and negative codebooks that are complements of each other, including by eliminating all candidate code words having negative disparity and filtering the remaining candidate code words in automated fashion based on predetermined spectral properties to select a subset of the candidate code words as the code words of the positive codebook. Preferably, all but a small subset of the (N+1)-bit code words (determined by a primary mapping) can be decoded by simple logic circuitry, and the remaining code words (determined by a secondary mapping) can be decoded by other logic circuitry or table lookup.

Abstract: A new scheme to transfer bidirectional data streams between a digital display and a computer is disclosed. This bidirectional data transfer can make several I/O devices attach to a display. Existing digital display interfaces are usually unidirectional from a computing to a display. Due to the nature of the existing clocking scheme, backward data transfer from the display side to the computer requires a backward clock. This invention discloses a scheme to send data bidirectionally without sending the additional backward clock. This invention also discloses a scheme to tolerate jitters from the clock source. With this approach, this new interface can make a digital display an I/O concentrator.

Abstract: A voltage controlled oscillator (“VCO”) circuit capable of generating signals with reduced jitter and/or low-phase noise is provided. One embodiment provides a plurality of cascaded VCO cells, where each VCO cell can include a source coupled differential pair, a bias transistor connected to the differential pair for biasing the differential pair, a resistive load pair connected to the differential pair, and a voltage controlled capacitor pair or varactor pair connected to the differential pair. The varactors provide control over the frequency of the oscillations produced by the VCO circuit in combination with a control voltage. A phase frequency detector combined with a charge pump and loop filter provide the control voltage.

Abstract: A versatile amplifier circuit for driving a TFT LCD panel is disclosed. The amplifier circuit of the present comprises consists of a complementary input stage, biasing switches, and a rail-to-rail output stage. A signal-transfer switch determines which of two differential amplifiers in the input stage will drive the output stage of the amplifier. A biasing signal precharges a capacitor between the gates of output stage. The rail-to-rail output stage utilizes the precharged capacitor to maintain a voltage required to operate the output stage properly. A polarity signal is used to control the signal-transfer switch. The polarity signal specifies if a lower half of the input stage or an upper half of the input stage is used to drive the output stage of the amplifier circuit. A non-active transistor is kept turned-on above the threshold voltage for quick switching of the output driver. In one embodiment, a coupling capacitor is used between output stage transistors is for this purpose.

Abstract: A method and system for establishing intensity levels for sub-pixels of a display device with overlapping logical pixels. The dithering system combines frame rate control techniques with contributions from overlapping pixels to establish the intensity level of each sub-pixel. The dithering system initially provides an assignment of frame numbers to each sub-pixel. The dithering system then receives a logical pixel color that includes an intensity value for each component color (e.g., red, green, and blue) for each logical pixel. The dithering system maps each component intensity value of each logical pixel to an intensity value with a low depth plus a remainder. The dithering system generates a sub-pixel intensity value for each sub-pixel of each logical pixel using frame rate control to adjust the intensity value of each sub-pixel based on the remainder and current frame number.

Abstract: Embodiments of a clock and data recovery method and apparatus include receiving a multi-channel serial digitally encoded signal and converting the received signal to digital data, or set of binary characters. One embodiment includes determining whether a phase of a sampling circuit is appropriate to sample meaningful data from a received signal; if the phase of the sampling circuit is not appropriate, the phase is shifted so that sampling occurs earlier or later for the received signal. The determination is based, in one embodiment, on the order and value of the samples taken, which indicate whether the samples are taken too close to a transition of the received signal.