Abstract: A chemical bath having liquid level indications in an outer trough is disclosed. The present invention adds an aqueduct in the outer bath of the chemical bath, and the chemical treatment liquid could flow into the aqueduct. According to the Pascal's law, the liquid level of the chemical treatment liquid in the aqueduct is the same with the liquid level of the chemical treatment liquid in the outer bath. Therefore, the level height of the chemical treatment liquid in the outer bath is observed from the transparent aqueduct by the naked eyes. The present invention abridges the complicated checkup steps, so that the producing time of apparatuses is increased and the amount of the wastes chemicals is decreased.

Abstract: A current output circuit for use in a digital-to-analog converter is disclosed. The current output circuit includes a current source for providing a driving current, and a first output circuit coupled with the current source. The first output circuit includes a first metal-oxide semiconductor (MOS) transistor device having a source electrode thereof connected to the current source in series, a first voltage amplifier coupled between the source electrode and a gate electrode of the first MOS transistor device for keeping a voltage of the source electrode substantially constant, and a first controlled switch coupled between an operational voltage and the gate electrode of the first MOS transistor device for being switched ON or OFF in response to a first digital control signal, and allowing the driving current to be outputted from a drain electrode of the MOS transistor device when the first controlled switch is switched ON.

Abstract: A fast line drawing method. First, the coordinates of two end points are received and a current point is assigned to one of the end points. The differences of x and y coordinates (&Dgr;x and &Dgr;y) and the sum of error E are computed, the integer part of &Dgr;x over &Dgr;y is denoted as Q. The current point is checked to determine whether it has reached the end point. If not and the value of E is negative, a point at the current point is drawn. The y-coordinate of the current point and E are updated by (Y+1) and (E−2&Dgr;x) respectively if E is non-negative, a span of pixels from (X,Y) to (X+Q-1,Y) are drawn if the coordinate of last of Q points is less than the end point. Otherwise, a span of pixels from (X,Y) to (x2,Y) are drawn.

Abstract: A semiconductor testing apparatus including a server, a robot arm, a gearing unit, a drive unit, a transmission unit, a control unit and a testing head. The drive unit drives the gearing unit and the transmission unit so as to rotate the testing head. In addition, the control unit controls the driving speed and driving direction of the drive unit so as to control the rotation speed and rotation direction of the testing head.

Abstract: A culling method and module is provided to generate a culling decision for efficient culling a back-face triangle of a 3D graphics. The culling module includes a comparison circuit and a culling decision circuit. The comparison circuit compares the coordinates of three vertices of each triangle and then outputs the comparison results to the culling decision circuit. The culling decision circuit then generates a decision result by looking up a predetermined lookup table according to the comparison results and a pre-determined coordinate orientation signal.

Abstract: A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.

Abstract: A capacitor in which the lower electrode and an interconnect line are located at the same level. The capacitor includes a first conductive line and a second conductive line on a substrate located at the same level, wherein the second conductive line defines a capacitor region and is used as a lower electrode of the capacitor; an insulating layer on the substrate, the first conductive line, and the second conductive line; and a third conductive line on the insulating layer in the capacitor region such that the third conductive line is used as an upper electrode of the capacitor. Since the lower electrode and an interconnect line can be in-situ (concurrently) formed to be located at the same level, one mask can be omitted compared with the conventional method, and production costs can be reduced.

Abstract: A method of forming an identifying mark on a semiconductor wafer. The identifying mark, for example a bar code or a character of patterns or words, is formed on the side wall of the semiconductor wafer to avoid contamination and the creation of failure dies during the formation of the identifying mark.

Abstract: A method and system for rendering computer graphics display tear-free is provided by determining a safe region for each associated block transfer command in real time. In response to a request of a graphics application program, a block transfer type is determined according to relative positions of a destination bitmap, and a source bitmap on the frame buffer. The invention defines three block transfer types: a top-down block transfer type, a bottom-up block transfer type and a direct block transfer type. Each of these block transfer types has an associated block transfer command for issuing to a command queue. After receiving each associated block transfer command, a safe region for an associated block transfer command will be determined in real time. Then, information from a source bitmap is transferred to a destination bitmap when the position of the current scan line is within the determined safe region defined for the associated block transfer command.

Abstract: A method for removing the circumferential edge of a dielectric layer on a semiconductor wafer is disclosed. First, a semiconductor wafer having a dielectric layer on its upper surface is provided. Second, the semiconductor wafer is placed and secured on a susceptor. Third, the circumferential edge of the dielectric layer is removed by a ring cutter. Then, the semiconductor wafer is cleaned from its central portion to its edge portion by water jets.

Abstract: A method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns. A first dielectric layer is formed on the semiconductor substrate. Next, a second dielectric layer is formed on the first dielectric layer to generate a composite dielectric layer. The second dielectric layer has a dielectric constant (k) higher than that of the first dielectric layer, a hardness higher than that of the first dielectric layer, and a thickness less than that of the first dielectric layer. The steps of forming the first dielectric layer and second dielectric layer can be repeated at least 2 to 3 times to form a stacked dielectric layer.

Abstract: An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.

Abstract: An anti-aliasing process without sorting the polygons in depth order to improve the image quality in three-dimensional graphics system. This method comprises extra buffer memory than does a typical three-dimensional graphics display system. The Z buffer stores the depth value of nearest pixel in front Z buffer and depth value of secondary nearest pixels in back Z buffer. The color buffer stores foreground color and background color. A weighting value is used and stored in the frame buffer to blend the foreground color and the background nearest color. The weighting value is associated with each pixel, it indicates the percentage of coverage of a pixel. Every pixel in Z buffer test stage will update the depth of the nearest pixel and the depth of the second nearest in Z-buffer, foreground color and background color in the frame buffer and the weighting value according to the result of depth comparison.

Abstract: A method and apparatus for transmitting registered data onto a PCI bus is provided, which can reduce the delay time of manipulating the outgoing signals without greatly increasing the circuit complexity. The apparatus employee a 2R1W data buffer to send a current phase data and a next phase data one clock cycle ahead of the actual AD activity on PCI bus and use a multiplexer to select the current phase data or the next phase data according to a select signal. The select signal is outputted by a OR gate with IRDY# and TRDY# signals as its inputs. Then, the apparatus use a flip-flop to toggling the output signal of the multiplexer to the PCI bus at the actual AD activity. Therefore, the apparatus of the present invention not only reduce the delay time of manipulating the outgoing signals, but also is implemented with simple architecture.

Abstract: A method and a computer system are provided for using a portion of a local memory of a graphics card as an extensive memory of a system memory. When the computer system is rebooted, a portion of a local memory of a graphics card is claimed as an extensive memory of the system memory, and the local memory excluding the extensive memory is claimed a new local memory by a driver of the graphics card. The driver of the graphics card reports the new local memory capacity to an operating system of the computer. Then, a new system memory capacity including the extensive memory and the original system memory is claimed by a chipset of the computer system and reported to a memory sizing command of BIOS. Finally, if a memory access request is within the address range of the extensive memory, the memory access request is transmitted to the graphics card through AGP/PCI bus.

Abstract: An apparatus and a method for cleaning wafers with contact holes or via holes are provided. The apparatus for cleaning wafers comprises a first arm, a second arm, a fixing device, a rotating device and a spraying device. The fixing device, disposed on the first arm, fixes the wafer in a manner such that a surface of the wafer, with contact holes or via holes, faces downward. The rotating device, disposed above the fixing device, rotates the fixing device. The spraying device, disposed on the second arm in a manner such that the spraying device is located beneath the fixing device, sprays the water upwards to the surface of the wafer. By the apparatus and method according to the invention, the possibility of native oxide remaining in the contact holes or the via holes is greatly reduced. In addition, the removal of defects from the surface of the wafer is enhanced.

Abstract: A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.

Abstract: All memory commands are classified into two categories: background commands and foreground commands, depending on whether they are data related or not. The pointed background command and foreground commands are issued onto the DRAM bus at the earliest time when the required constrains are met. The background and foreground FSM controllers work in a pipelined or overlapped manner.

Abstract: A digital-to-analog converting method operating under two clock signals of different periods is disclosed. The method includes steps of monitoring a phase relationship between the two clock signals; starting transmission of a plurality of pre-stored series of waveform samples in response to each rising edge of the first clock signal, wherein a phase difference is present between every two adjacent series of waveform samples; outputting the waveform samples of each series in response to rising edges of the second clock signal; and selecting one of the plurality of pre-stored sets of waveform samples to be converted into an analog signal according to the phase relationship. The various pre-stored series of waveform samples having therebetween phase differences are optionally used for phase compensation so as to reduce the clock jitter between the two clock signals. A digital-to-analog converter for implementing the above-mentioned method is also disclosed.

Abstract: A method of reducing micro-scratches during tungsten CMP. Tungsten CMP with a standard tungsten slurry is first provided on the exposed surfaces of a tungsten plug and a IMD layer on a semiconductor substrate. The tungsten CMP with an oxide slurry is then provided on the polished surfaces of the tungsten plugs and the IMD layer.