Abstract: A receiver for a memory controller. The memory controller sends a data request signal to a memory which responds to the data request signal by sending data and a data strobe signal back to the memory controller. The receiver comprises a delay circuit receiving and delaying the data strobe signal, an emulated data strobe signal generator receiving the data request signal to generate an emulated data strobe signal, a push pointer generator generating a plurality of push pointers having priorities, receiving and responding to the emulated data strobe signal by outputting the push pointers in an order according to the priorities, and a buffer receiving and responding to the delayed data strobe signal and the push pointers by storing the data in memory addresses corresponding to the push pointers.

Abstract: An apparatus for line drawing using a plurality of pixels to display a line, including a first parameter generating module, a second parameter generating module, a storage module, a retrieving module, and a calculating module. In this case, the first parameter generating module generates a first parameter according to a slope of the line. The second parameter generating module generates a second parameter according to the distance between one of the pixels and the line in axial directions. The storage module stores an index table, which records at least a blending factor and the correlations between the first parameter, second parameter, and blending factor. Therefore, the retrieving module searches for the blending factor from the index table according to the first and second parameter. Finally, the calculating module determines the color of this pixel according to the blending factor.

Abstract: Voltage dividing resistors (R1a, R1b, R2a, R2b) are connected in parallel with diode connected bipolar transistors (Q1, Q2) for splitting the voltage to the inputs of an operational amplifier (62, 82). Current is provided to this arrangement by current sources (I1, I2). When the supply voltage is about 0.85 volts, a temperature insensitive reference voltage of about 200 millivolts is available at the drain of a second transistor (M2, M2).

Abstract: A method is adapted for compressing an image data block, and includes the steps of: (a) subjecting the image data block to discrete cosine transformation so as to generate discrete cosine transform data; (b) quantizing the discrete cosine transform data in accordance with a quantizer matrix that consists of an array of quantizing coefficients so as to generate quantized data; (c) encoding the quantized data using an entropy coding algorithm so as to generate an encoded bitstream; and (d) when the length of the encoded bitstream does not fall within a predetermined range, adjusting the quantizing coefficients in the quantizer matrix and repeating steps (b) and (c) until the length of the encoded bitstream falls within the predetermined range.

Abstract: A die paddle for receiving an integrated circuit die in a plastic substrate. The die paddle is defined by a copper film on the plastic substrate and comprises a plurality of via holes through the plastic substrate, a plurality of opening through the copper film, and a gold-containing ring formed on the peripheral portion of the copper film. The outermost openings (and/or the outermost via holes) and the gold-containing ring are separated by a distance of about 1 to about 20 mils.

Abstract: A transmission mode detector for digital receiver is proposed. The transmission mode detector comprises a RF tuner for receiving RF signals and generating intermediate frequency (IF) signals. An envelope detector is employed to filter the IF signals and generate rough envelope signal and a hard-decision machine is employed to quantize the rough envelope signal into hard-decision binary signals. The transmission mode detector further comprises a glitch remover to remove the unwanted glitch in the binary signals and generate envelope signal. An A/D converter is used to quantize the IF signals and generate digital signal. Further more, an I/Q de-multiplexer is used to extract the in-phase and the quadrature terms of the OFDM symbol from the digital signal. The transmission mode detector then detects the transmission mode by a mode detect unit according to the period of the envelope signal.

Abstract: A padless high density circuit board and manufacturing method thereof. The method includes providing a circuit board substrate, forming external wiring, having a plurality of external terminals with a width as large as or less than the external wiring on the circuit board substrate, forming a solder mask over the circuit board substrate and the external wiring with a plurality of solder mask openings exposing the external terminals, with diameters at least as large as the widths of the external terminals exposed thereby, and forming a plurality of conductive bumps on the external terminals exposed by the solder mask openings for connection with an external device in a subsequent assembly process.

Abstract: The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.

Abstract: A fast line drawing method. First, the coordinates of two end points are received and a current point is assigned to one of the end points. The differences of x and y coordinates (?x and ?y) and the sum of error E are computed, the integer part of ?x over ?y is denoted as Q. The current point is checked to determine whether it has reached the end point. If not and the value of E is negative, a point at the current point is drawn. The y-coordinate of the current point and E are updated by (Y+1) and (E?2?x) respectively if E is non-negative, a span of pixels from (X,Y) to (X+Q?1,Y) are drawn if the coordinate of last of Q points is less than the end point. Otherwise, a span of pixels from (X,Y) to (x2,Y) are drawn.

Abstract: An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write parts of the FIFO, wherein n is any integer more than one. Additional binary counters are used to accumulate the read and write overflows for the circular Gray code counters. When any circular Gray code counter is overflow, the read or write count is transferred to the respective binary counter for recording the FIFO accesses.

Abstract: A method is provided to reduce strapping devices in a computer system having at least one configurable device, which includes the following steps. A configuration value stored in a non-volatile memory is first provided. During power-up and reset of the computer system, a processor reset signal and a bus reset signal of a high-speed peripheral bus are both asserted, wherein the high-speed peripheral bus is included in the computer system. When an operation clock of the high-speed peripheral bus reaches its working voltage and frequency, the configuration value is fetched from the non-volatile memory. The fetching step is repeated until a most significant bit (MSB) of a fetched configuration value changes from a first state to a second state.

Abstract: A chip-packaging substrate. The substrate is capable of reducing damage during packaging, shrinking its connecting portions so that the length of any of the gap slots between the packaging portion and the frame portion of the substrate is increased. Furthermore, a dummy layer is provided to one surface of the frame portion to flush the surface on the frame portion with that of the packaging portion as much as possible.

Abstract: An apparatus and a method for supporting coexistence of an external AGP graphics adapter with an embedded graphics adapter. The embedded graphics adapter may be regarded as a PCI device, and the graphics memory of embedded graphics adapter is integrated into DRAM of a computer system. The corelogic and software capable of graphics address remapping and directed accessing graphics memory of the embedded graphics adapter for supporting external AGP graphics adapter and embedded graphics adapter respectively. The embedded graphics adapter could be an AGP device while the external graphics adapter would be a PCI device, and vice versa.

Abstract: A multiplying digital-to-analog converter (MDAC) stage includes a plurality of second capacitances in parallel selectively connected between an input node and an amplifier input and between a corresponding plurality of digital reference signals, which can include a pseudo-random first calibration signal, and the amplifier input. A pipelined ADC incorporating a series of such MDAC stages includes a multiplier connected to the last MDAC stage of the series, a low-pass filter for filtering output of the multiplier and outputting a DC component, and an encoder for receiving output of the MDAC stages and generating a digital output signal and for compensating the digital output signal with the DC component. Background calibration of the ADC includes applying the first calibration signal to a second capacitance of the MDAC stage during a hold phase, and filtering the first calibration signal from the digital output of the pipelined analog-to-digital converter.

Abstract: A digital picture processing method for mainly partitioning an inputted picture into a plurality of blocks and then separately performing a deblocking process and a deringing process on each of the blocks so as to reduce the required memory space and to instantaneously process the data.

Abstract: The invention relates to a method for detecting video frame types with median filtering, which proceeds a denoising step after caculating the comb factor of each pixel, to avoid incorrect judgment of the frame type resulting from excessive field difference and improve detection accuracy.

Abstract: A method for motion pixel detection with adaptive thresholds, according to the global motion information among the reference video fields, so as to correctly evaluate whether a missing pixel is in a static region or a non-static region, thereby reconstructing the missing pixel by an inter-field interpolation process or an intra-field interpolation process. If the amount of motion among the reference fields is large, there is high motion information among the reference fields, so the threshold is set to be small; if the amount is small, there is less motion information between the reference fields, and so the threshold should be set to be large.

Abstract: A method for adjusting sharpness and brightness of a digital image. In this method, an image function is first inputted into a processor. The image function comprises a plurality of control parameters. Next, the control parameter values of the control parameters are set, and then each of the pixels is sequentially leaded into the image function according to the control parameter value so as to perform the corresponding operation for adjusting the sharpness and brightness of the image. Finally, the adjusted image is outputted. Therefore, the two processes in the prior art, one for adjusting the brightness, the other for the sharpness, are merged into one process so that the design of the hardware circuit is simplified and the required memory space is reduced.

Abstract: A method for motion pixel detection with a static counter map so as to correctly evaluate whether a missing pixel is in a static region or a non-static region, thereby reconstructing the missing pixel by an inter-field interpolation process or an intra-field interpolation process, respectively.

Abstract: A semiconductor memory with a sense amplifier for high-speed sensing of the signal from a memory cell. The semiconductor memory includes plural memory arrays having plural memory cells, a sense amplifier, and a latch circuit. The memory cells are precharged when a precharge signal is enabled. The sense amplifier has an additional discharge path enabled by the disabled precharge signal to speed up reading data. The latch circuit is turn off by the enabled precharged signal to hold the data.