Abstract: A method for a 3:2 pull-down film source detection. First, a source is received. Then, field differences of two fields of the same type in the source and an average field difference according to the field difference corresponding to at least one prior field in the source are calculated. The source is established as a 3:2 pull-down film source by checking whether a 3:2 pull-down signature is in the source according to the field difference and the average field difference, and a bad editing point is detected according to an interlaced frame information of the source.

Abstract: A routing method for routing a plurality of signal traces out of a plurality of corresponding bumper pads in a multi-layer circuit board. The multi-layer circuit board includes at least a first layer and a second layer. The method includes arranging the plurality of bumper pads based on a plurality of triangle units, routing a plurality of signal traces out of a plurality of corresponding bumper pads of in the first layer, routing a plurality of signal traces out of a plurality of corresponding bumper pads in the second layer not to be vertically parallel with the plurality of signal traces routed in the first layer, and arranging a plurality of shielding traces among the plurality of signal traces in the first layer and in the second layer.

Abstract: An equalization method and device for equalizing the received vestigial sideband (VSB) signal, utilizes segment-sync symbols, Sato directions, erasure slicers, and variable step-sizes. In addition to stop-and-go (SAG) mode, the directions of Sato errors can also be used for speed up the convergence of tap weights of the equalizer. Erasure slicers can mitigate the effect of decision errors as they are passed through the feedback filter. In time-variant environments, variable step-sizes help the equalizer tracking the variations of the channels; in time-invariant environments, variable step-sizes help ease the fluctuations of the steady-state equalizer tap weights, and therefore yield smaller mean-squared-error and better symbol error rate (SER).

Abstract: An apparatus for generating an interleaved stereo image includes a 3D graphics engine, an interleaved data merger and a register. The 3D graphics engine generates a shrunken left-eye image and a shrunken right-eye image of a stereo image based on video source data, the vertical sizes of the shrunken left-eye image and the shrunken right-eye image are shrunk compared with the vertical size of the video source data. The interleaved data merger stores the shrunken left-eye image and the shrunken right-eye image into two consecutive memory segments, and scans the memory segments while displaying the stereo image. A register controls a line number of a display region, so that the rows of the left-eye image shrunk and the right-eye image shrunk arrive at the display region in line-interleaved order. The invention also discloses a method for generating an interleaved stereo image.

Abstract: A method for motion pixel detection with a static counter map so as to correctly evaluate whether a missing pixel is in a static region or a non-static region, thereby reconstructing the missing pixel by an inter-field interpolation process or an intra-field interpolation process, respectively.

Abstract: A carrier recovery apparatus for digital Quadrature Amplitude Modulation (QAM) receivers is disclosed. The carrier recovery apparatus includes a phase detector, a lock controller, a frequency locker and a phase loop filter, and provide phase/frequency error information for a numerically controlled oscillator (NCO) to generate recovered carrier frequency. The phase detector detects the symbol energy information and the phase error information of the extracted symbols from the I/Q extractor. The lock controller monitors the symbol energy from the phase detector, separates the extracted symbols into two groups: valid and non-valid, and outputs the control flag of valid symbols into both the frequency locker and the phase loop filter. To achieve a wide range acquisition and a good tracking performance, the lock controller controls the operation of the frequency locker and the phase loop filter in three operations.

Abstract: The present invention provides a multi-stage delay clock generator including: a plurality of delay cells, each delay cell generating a delay signal to a subsequent delay cell in response to a delayed clock signal from a preceding delay cell and a delay control signal where a first delay cell among the plurality of delay cells receives an external clock signal, and each subsequent delay cell comprises a smaller delay step than the current delay cell; a phase detector, responsive to the external clock signal and a feedback clock signal, for generating a lock control signal; an integrator, responsive to the lock control signal, for generating the delay control signal; and a control unit for programming the delay cells.

Abstract: A distributed video stream decoding system on computer and decoding method of the system is proposed to increase the decoding efficiency. The decoding method reads pictures of video stream and divides each picture into a plurality of slice packages through software modules executing on a CPU. Then, the method dispatches the slice packages by slice dispatcher and sends at least a slice into a master decoder when the slice queue of the master decoder less then a default value and sends a slice into a secondary decoder when the secondary decoder is waiting, respectively. Therefore, the master decoder and the secondary decoder can decode the received slice simultaneously to increase the decoding efficiency.

Abstract: An low-voltage triggered PNP device for input signals with voltage level larger than VDD or less than VSS. The ESD protection device provides an ESD path from a first to a second node for protection of an internal circuit. The device comprises a substrate of a first conductivity type coupled to the first node, a first doped region of a second conductivity type in the substrate, wherein the first doped region is floated, a second doped region of the first conductivity type in the first doped region coupled to the second node, and a third doped region in the substrate, adjacent to the first doped region, to have a low trigger voltage.

Abstract: A collision detection method for a multiple access communication system is disclosed. By using the error term of a time-domain equalized signal as a detection source, an operation on the error term can be performed to determine whether collision occurs. For example, the mean square error and/or maximum value of the real part and/or imaginary part of the error term can be calculated or selected to distinguish the collision and non-collision situations. A collision detection apparatus for a multiple access communication system is also disclosed. The collision detection apparatus utilizes an existent adaptive equalizer and signal processing device for obtaining received information data bits to obtain the error term. The error term is further processed by a mean-square-error or maximum-absolute-value operator to determine the collision status.

Abstract: A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

Abstract: A method for detecting dynamic video pixels by using adaptive counter threshold values according to field difference value of the frame in the video, thereby to determine whether the frame is an interlaced frame or a progressive frame and to eliminate incorrect judgements resulting from field difference and to improve accuracy of frame determination.

Abstract: A subtractor is connected between a p-channel bandgap reference unit and an n-channel bandgap reference unit. The subtractor includes two NPN transistors connected to the p-channel bandgap reference unit, and two PNP transistors connected to the n-channel bandgap reference unit. The subtractor takes the difference of the two currents produced by the p-channel and n-channel bandgap reference units and generates a temperature insensitive and curvature-compensated reference voltage of less than one volt across an output resistor.

Abstract: An apparatus for computing a logarithm to a base p of a floating-point number X. The floating-point number X is represented in the format of (?1)Sx·2Ex·Mx, where Mx=(1+fx)=(1+Ax·2?K)+(Bx·2?N), where Sx is a sign, Ex is an exponent, Mx is a mantissa, 1?Mx<2, fx is a N-bit fraction, Ax is a value of the most significant K bits of fx, Bx is a value of the least significant (N?K) bits of fx, 0?K<N, and p, K, N are natural numbers. The apparatus includes: a first multiplier, a logarithmic table, a first adder, a divider, a Taylor-Series approximation circuit, a second multiplier, and a second adder.

Abstract: A method is provided to reduce clock skew in an integrated circuit having a number of circuit blocks, which comprises the following steps. A first source clock coupled to a clock input terminal of a first circuit block within the circuit blocks is provided, as is a second source clock coupled to a clock input terminal of a second circuit block within the circuit blocks. When the second circuit block is configured to operate in synchronization with the first circuit block, the clock input terminal of the second circuit block is switched to the first source clock, and thus both the first circuit block and the second circuit block can operate in accordance with the same first source clock.

Abstract: A method for adjusting sharpness and brightness of a digital image. In this method, an image function is first inputted into a processor. The image function comprises a plurality of control parameters. Next, the control parameter values of the control parameters are set, and then each of the pixels is sequentially leaded into the image function according to the control parameter value so as to perform the corresponding operation for adjusting the sharpness and brightness of the image. Finally, the adjusted image is outputted. Therefore, the two processes in the prior art, one for adjusting the brightness, the other for the sharpness, are merged into one process so that the design of the hardware circuit is simplified and the required memory space is reduced.

Abstract: The invention provides a semiconductor package substrate, which includes a substrate, a chip contact area, an inner pad portion, an outer pad portion and a conductive layer. The chip contact area, the inner pad portion, the outer pad portion and the conductive layer are formed on one side of the substrate, wherein the outer pad portion encloses the inner pad portion that surrounds the chip contact area in the center of the substrate. The inner pad portion and the outer pad portion contain a plurality of signal pads and a plurality of shielding pads respectively, while the conductive layer and each of the shielding pads are electrically connected.

Abstract: An apparatus for calculating an exponential calculating result for a base 2 floating-point number comprises a transforming device, K exponential tables and a multiplier. The transforming device receives the floating-point number, transforms the floating-point number to an integer part and a fractional part and outputs the integer part and the fractional part. The fractional part is an N-bit number and divided into K parts which have N1, N2, . . . , NK bits respectively, wherein N=N1+N2+ . . . +NK. Each of the exponential tables receives one of the K parts divided from the fractional part and outputs a result. The multiplier receives all results from the exponential tables and outputs a mantissa. The integer part outputted form the transforming device is an exponent.

Abstract: An approach to enhance the noise immunity of high-speed digital signals by means of a resonance-free environment is developed. Resonance detuning is achieved by appropriately reshaping the layout of the power/ground planes. Resonant properties of the power distribution system, including resonant frequencies and field distribution profiles, were characterized with frequency-domain simulations. Analysis of the resonant field profiles reveals that the electric field distribution of the dominant mode normally concentrates in the vicinity of the plane edge. Therefore, resonance can be effectively tuned out of the operating frequency range through boundary configuring. In addition, it is shown that variation of the quality factor with the external probe position provides a means to monitor and construct the resonant field distribution. Physical mechanism responsible for this unique property is clarified from the perspective of probe coupling.

Abstract: This disclosure presents a heat dissipation mechanism, which conducts generated heat of a thermal device to the housing of an electronic apparatus by a metal piece fastened between the thermal device and electronic apparatus, and then dissipates heat into the air through multiple holes opened over an apparatus shell. Besides, the presented mechanism is also suitable to mini-size, portable electronic apparatus to solve the thermal dissipation technique thereof.