Abstract: In one embodiment, the present invention includes a method for determining process corner information of an integrated circuit (IC) and controlling at least one analog current for at least one analog circuit of the IC based on the process corner information. More specifically, if the process corner information is indicative of a fast corner IC, the analog current may be scaled down. At the same time that the analog current is scaled down, a current consumption level of digital circuitry of the IC may increase. In this way, overall power consumption of the IC may be reduced to the extent that the analog current(s) are scaled.

Abstract: A method is disclosed that includes receiving a classification voltage at a powered device from a network. The classification voltage includes a baseline voltage level that is below an operating voltage range of the powered device and includes a sequence of distinct signal elements derived from the classification voltage. The method further includes detecting a number of signal elements of the sequence of distinct signal elements. A current is drawn until the number of signal elements exceeds a predetermined number.

Abstract: A microelectromechanical systems (MEMS) device includes a tuning electrode, a drive electrode, and a resonator. The resonator is anchored to a substrate and is configured to resonate in response to a signal on the drive electrode. The MEMS device includes a tuning plate coupled to the resonator and positioned above the tuning electrode. The tuning plate is configured to adjust a resonant frequency of the resonator in response to a voltage difference between the resonator and the tuning electrode. In at least one embodiment of the MEMS device, the tuning plate and the tuning electrode are configured to adjust the resonant frequency of the resonator substantially independent of the signal on the drive electrode.

Abstract: In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.

Abstract: In one embodiment, the present invention includes a single chip radio tuner, which may be adapted within an integrated circuit (IC). The tuner may be provided with a configurable front end to receive and process a radio frequency (RF) signal via a signal path. This configurable front end may be differently controlled depending on a particular radio implementation in which the tuner is adapted.

Abstract: In one embodiment, a second-order delta-sigma analog-to-digital converter (ADC) includes a second-order integrator adapted to second-order integrate a value at a first node, where the first node is coupled to an input of the ADC. The ADC also includes a comparator coupled to an output of the second-order integrator. The ADC further includes a digital-to-analog converter (DAC) coupled between an output of the comparator and the first node. The DAC is adapted to receive a digital output of the comparator and to generate a first charge or a second charge. The DAC includes a first charge pump adapted to produce the first charge and a second charge pump adapted to produce the second charge. The first and second charges are asymmetric.

Abstract: An oscillator output is controlled from an external voltage control terminal using an interpolative divider as a frequency modulator. The oscillator includes a reference clock generator, analog to digital converter, and an interpolative divider. Nominal output frequency is determined by the frequency of the reference clock and the nominal divide value of the interpolative divider. The divide value is changed according to the voltage control input value which is converted to a digital value via an analog to digital converter. Multiple interpolative dividers may be coupled to the single reference clock generator and each have a voltage control input and analog to digital converter.

Abstract: In one embodiment, the present invention includes an apparatus having a first pair of low voltage operational amplifiers to generate an output representative of an absolute value difference of first and second line voltages of a subscriber loop, and a third low voltage operational amplifier having an input coupled to the output of the first pair of low voltage operational amplifiers to filter the output and to provide a switch control signal for a switching regulator that provides a voltage used to generate the first and second line voltages. The apparatus may include additional circuits such as a limit circuit to limit the input to the third low voltage operational amplifier and one or more speedup circuits to reduce a filter time constant of the third low voltage operational amplifier during a ringing mode of the subscriber loop.

Abstract: Integrated low-IF (low intermediate frequency) data receivers and associated methods are disclosed that provide advantageous and cost-efficient solutions.

Abstract: A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.

Abstract: A crystal offset value is stored in non-volatile memory in an oscillator device. The crystal offset value corresponds to a ratio between a rated frequency of an output of a crystal oscillator and a measured frequency of the output of the crystal oscillator. A rated divide value that corresponds to a selected frequency for an output of the oscillator device assumes the crystal oscillator operates at its rated or ideal frequency. Thus, the rated divide value corresponds to the rated frequency. The rated divide value is adjusted by the crystal offset value to generate an adjusted divide value and the adjusted divide value is used to generate an output signal of the oscillator device with the selected frequency.

Abstract: A low-noise amplifier (LNA) includes an input terminal for receiving an input signal, an output terminal for providing an output signal related to the input signal. The LNA further includes a first transistor having a first source coupled to the input terminal through the first capacitor, a first gate configured to receive a first direct current (DC) bias signal, and a first drain coupled to the output terminal. The LNA also includes a second transistor having a second source coupled to the input terminal through the second capacitor, a second gate configured to receive a second DC bias signal, and a second drain coupled to the output terminal.

Abstract: A multi-standard single-chip receiver for digital demodulation of TV signals broadcasted over any of multiple digital television means, e.g., satellite, cable and terrestrial, is provided. The receiver can receive and demodulate a variety of different signal types received from one or more up-front tuners. A demodulator architecture in accordance with an embodiment of the present invention can be optimized to re-use common demodulation processing blocks for the different incoming signal types.

Abstract: A low-noise amplifier includes first and second transconductance paths and first and second variable capacitive dividers. The first transconductance path has a first terminal for receiving a first input signal, a control terminal, and a second terminal for providing a first output signal. The second transconductance path has a first terminal for receiving a second input signal, a control terminal, and a second terminal for providing a second output signal. The first variable capacitive divider has a first terminal for receiving the first input signal, a second terminal coupled to a reference voltage terminal, and an intermediate terminal coupled to the control terminal of the second transconductance path. The second variable capacitive divider has a first terminal for receiving the second input signal, a second terminal coupled to the reference voltage terminal, and an intermediate terminal coupled to the control terminal of the first transconductance path.

Abstract: In an embodiment, an electrical over-stress (EOS) circuit includes a detection circuit coupled between first and second supply terminals and configured to detect a perturbation in a supply voltage potential between the first and second supply terminals or between a supply voltage potential and a pad voltage of a bond pad. The EOS circuit further includes an alert generation circuit configured to store data indicating an EOS event in response to detecting the perturbation.

Abstract: A communications device is provided. The communications device includes first output stage circuitry configured to generate a first radio frequency (RF) output signal in response to receiving an RF input signal, a first antenna port configured to couple to a first antenna and configured receive the first RF output signal from the first output stage circuitry, second output stage circuitry configured to generate a second RF output signal in response to receiving the first RF output signal, and a second antenna port configured to couple to a second antenna and configured to receive the second RF output signal from the second output stage circuitry. The first output stage circuitry, the first antenna port, the second output stage circuitry, and the second antenna port are at least partially integrated on the same integrated circuit.

Abstract: In various implementations, a re-configurable phase lock loop may have multiple signal paths, including a feedforward path to operate in a carrier frequency acquisition mode to obtain a carrier frequency estimate and a feedback loop path to operate in a carrier frequency tracking mode to translate an incoming signal to a baseband signal. The multiple signal paths may share most of the hardware to reduce implementation cost.

Abstract: Systems and methods are disclosed that use multiple DC-DC (direct-current-to-direct-current) regulators and configurable DC-DC regulators with respect to multi-band audio receivers in order to allow for the use of different DC-DC regulator switching clock signals for different audio broadcast bands. The systems and methods disclosed thereby help to alleviate interference problems typically caused by switching devices used in the DC-DC conversion process. The embodiments described are also applicable to switching power supplies run from alternating current (AC) power sources and to Class D amplifiers working with broadcast radios.

Abstract: An integrated circuit (500) includes a semiconductor substrate (400) and an integrated circuit package (530). The semiconductor substrate (400) has a first pair of bonding pads (442, 444) conducting a differential output signal thereon and adapted to be coupled to an input of a first external filter, and a second pair of bonding pads (452, 454) conducting a differential input signal thereon and adapted to be coupled to an output of said first external filter. The integrated circuit package (530) encapsulates the semiconductor substrate (400) and has first (452, 454) and second (552, 554) terminal pairs corresponding and coupled to the first (442, 444) and second (452, 454) pairs of bonding pads, respectively. The first (452, 454) and second (552, 554) terminal pairs are separated by a first predetermined distance is sufficient to maintain an input-to-output isolation therebetween of at least a first predetermined amount.

Abstract: A radio frequency (RF) receiver comprises an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal. The digital processor controls a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the digital processor on the analog receiver.